74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 08 — 6 November 2008
Product data sheet
1. General description
The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting
3-state bus compatible outputs in both send and receive directions. The device features
two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for
direction control. nOE controls the outputs so that the buses are effectively isolated. This
device can be used as two 8-bit transceivers or one 16-bit transceiver.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features
I
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I
I
I
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I
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5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
All data inputs have bus hold. (74LVCH16245A only)
Complies with JEDEC standard JESD8-B / JESD36
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
CDM JESD22-C101C exceeds 1000 V
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
I
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range Package
Name
74LVC16245ADL
74LVCH16245ADL
74LVC16245ADGG
74LVCH16245ADGG
74LVC16245AEV
74LVCH16245AEV
74LVC16245ABQ
74LVCH16245ABQ
−40 °C
to +125
°C
−40 °C
to +125
°C
VFBGA56
−40 °C
to +125
°C
TSSOP48
−40 °C
to +125
°C
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5
×
7
×
0.65 mm
SOT1025-1
HUQFN60U plastic thermal enhanced ultra thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 x 6 x 0.55 mm
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Fig 1.
Logic symbol
74LVC_LVCH16245A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 6 November 2008
2 of 19
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
1OE
1DIR
2OE
2DIR
G3
3EN1[BA]
3EN2[AB]
G6
6EN1[BA]
6EN2[AB]
1A0
1
2
1B0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aaa790
Fig 2.
IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
74LVC_LVCH16245A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 6 November 2008
3 of 19
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
74LVC16245A
74LVCH16245A
1DIR
1B0
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1
2
3
4
5
6
7
8
9
48
1OE
47
1A0
46
1A1
45
GND
44
1A2
43
1A3
42
V
CC
41
1A4
40
1A5
39
GND
38
1A6
37
1A7
36
2A0
35
2A1
34
GND
33
2A2
32
2A3
31
V
CC
30
2A4
29
2A5
28
GND
27
2A6
26
2A7
25
2OE
001aad110
GND
10
1B6
11
1B7
12
2B0
13
2B1
14
GND
15
2B2
16
2B3
17
V
CC
18
2B4
19
2B5
20
GND
21
2B6
22
2B7
23
2DIR
24
74LVC16245A
ball A1
74LVCH16245A
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
001aad111
Transparent top view
Fig 4.
Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 5.
Pin configuration SOT702-1 (VFBGA56)
74LVC_LVCH16245A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 6 November 2008
4 of 19
NXP Semiconductors
74LVC16245A; 74LVCH16245A
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B15
B16
B17
A25
A24
A23
A22
74LVC16245A
74LVCH16245A
B14
A21
B13
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aai894
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 6.
Pin configuration SOT1025-1 (HUQFN60U)
74LVC_LVCH16245A_8
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 08 — 6 November 2008
5 of 19
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