Features
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80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
ISP (In-system Programming) Using Standard V
CC
Power Supply
Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– 16K/32K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100K Write Cycles
On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 Bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
Keyboard Interrupt Interface on Port P1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Programmable Counter Array 5 Channels
– High-speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full Duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-out)
Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
Packages: PDIL40, PLCC44, VQFP44
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8-bit
Microcontroller
with 16K/
32K Bytes Flash
AT89C51RB2
AT89C51RC2
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Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro-
controllers. It contains a 16K or 32K Bytes Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
Rev. 4180E–8051–10/06
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/counters.
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of
1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a
more versatile serial channel that facilitates multiprocessor communication (EUART)
and a speed improvement mechanism (X2 mode).
The Pinout is the standard 40/44 pins of the C52.
The fully static design reduces system power consumption of the AT89C51RB2/RC2 by
allowing it to bring the clock frequency down to any value, even DC, without loss of data.
The AT89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8-bit
clock prescaler for further reduction in power consumption. In Idle mode, the CPU is fro-
zen while the peripherals and the interrupt system are still operating. In power-down
mode, the RAM is saved and all other functions are inoperative.
The added features of the AT89C51RB2/RC2 make it more powerful for applications
that need pulse width modulation, high speed I/O and counting capabilities such as
alarms, motor control, corded phones, and smart card readers.
Table 1.
Memory Size
Part Number
AT89C51RB2
AT89C51RC2
AT89C51IC2
Flash (Bytes)
16K
32K
32K
XRAM (Bytes)
1024
1024
1024
TOTAL RAM
(Bytes)
1280
1280
1280
I/O
32
32
32
2
AT89C51RB2/RC2
4180E–8051–10/06
AT89C51RB2/RC2
Block Diagram
Figure 1.
Block Diagram
T2EX
PCA
RxD
TxD
Vss
V
CC
ECI
T2
(1)
SPI
(1) (1) (1) (1)
MISO
P1
P2
P3
MOSI
SCK
P0
(2) (2)
XTAL1
XTAL2
(1)
Boot
ROM
2Kx8
(1) (1)
EUART
+
BRG
RAM
256x8
Flash
32Kx8 or
16Kx8
XRAM
1Kx8
PCA
Timer2
ALE/ PROG
PSEN
CPU
EA
RD
WR
(2)
(2)
C51
CORE
IB-bus
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
Watch Key
Dog Board
(2) (2)
T0
RESET
T1
(2) (2)
INT0
INT1
Notes:
1. Alternate function of Port 1.
2. Alternate function of Port 3.
SS
3
4180E–8051–10/06
SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following
categories:
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C51 core registers: ACC, B, DPH, DPL, PSW, SP
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
Power and clock control registers: PCON
Hardware Watchdog Timer registers: WDTRST, WDTPRG
Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1
Keyboard Interface registers: KBE, KBF, KBLS
SPI registers: SPCON, SPSTR, SPDAT
BRG (Baud Rate Generator) registers: BRL, BDRCON
Flash register: FCON
Clock Prescaler register: CKRL
Others: AUXR, AUXR1, CKCON0, CKCON1
4
AT89C51RB2/RC2
4180E–8051–10/06
AT89C51RB2/RC2
Table 2.
C51 Core SFRs
Mnemonic
ACC
B
PSW
SP
DPL
DPH
Add
E0h
F0h
D0h
81h
82h
83h
Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer Low Byte
Data Pointer High Byte
CY
AC
F0
RS1
RS0
OV
F1
P
7
6
5
4
3
2
1
0
Table 3.
System Management SFRs
Mnemonic
PCON
AUXR
AUXR1
CKRL
CKCKON0
CKCKON1
Add
87h
8Eh
A2h
97h
8Fh
AFh
Name
Power Control
Auxiliary Register 0
Auxiliary Register 1
Clock Reload Register
Clock Control Register 0
Clock Control Register 1
7
SMOD1
DPU
-
CKRL7
-
-
6
SMOD0
-
-
CKRL6
WDTX2
-
5
-
M0
ENBOOT
CKRL5
PCAX2
-
4
POF
XRS2
-
CKRL4
SIX2
-
3
GF1
XRS1
GF3
CKRL3
T2X2
-
2
GF0
XRS0
0
CKRL2
T1X2
-
1
PD
EXTRAM
-
CKRL1
T0X2
-
0
IDL
AO
DPS
CKRL0
X2
SPIX2
Table 4.
Interrupt SFRs
Mnemonic
IEN0
IEN1
IPH0
IPL0
IPH1
IPL1
Add
A8h
B1h
B7h
B8h
B3h
B2h
Name
Interrupt Enable Control 0
Interrupt Enable Control 1
Interrupt Priority Control High 0
Interrupt Priority Control Low 0
Interrupt Priority Control High 1
Interrupt Priority Control Low 1
7
EA
-
-
-
-
-
6
EC
-
PPCH
PPCL
-
-
5
ET2
-
PT2H
PT2L
-
-
4
ES
-
PHS
PLS
-
-
3
ET1
-
PT1H
PT1L
-
-
2
EX1
ESPI
PX1H
PX1L
SPIH
SPIL
1
ET0
EI2C
PT0H
PT0L
IE2CH
IE2CL
0
EX0
KBD
PX0H
PX0L
KBDH
KBDL
Table 5.
Port SFRs
Mnemonic
P0
P1
P2
P3
Add
80h
90h
A0h
B0h
Name
8-bit Port 0
8-bit Port 1
8-bit Port 2
8-bit Port 3
7
6
5
4
3
2
1
0
5
4180E–8051–10/06
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