A3938
Three-Phase Power MOSFET Controller
The A3938 is a three-phase, brushless dc motor controller. The A3938
high-current gate drive capability allows driving of a wide range of
power MOSFETs and can support motor supply voltages to 50 V. The
A3938 integrates a bootstrapped high-side driver to minimize the exter-
nal component count required to drive N-channel MOSFET drivers.
Internal
fi
xed off-time, PWM current-control circuitry can be used to
regulate the maximum load current to a desired value. The peak load
current limit is set by the user’s selection of an input reference volt-
age and external sensing resistor. A user-selected external RC timing
network sets the
fi
xed off-time pulse duration. For added
fl
exibility, the
PWM input can provide speed/torque control where the internal current
control circuit sets a limit on the maximum current.
The A3938 includes a synchronous rectification feature. This shorts out
the current path through the power MOSFET reverse body diodes dur-
ing PWM off-cycle current decay. This can minimize power dissipation
in the MOSFETs, eliminate the need for external power clamp diodes,
and potentially allow a more economical choice for the MOSFET drivers.
The A3938 provides commutation logic for Hall sensors configured for
120-degree spacing. The Hall input pins are pulled-up to an internally-
generated 5 V reference. Power MOSFET protection features include:
bootstrap capacitor charging current monitor, regulator undervoltage
monitor, motor lead short-to-ground, and thermal shutdown.
The LD package is available in a lead-free version (100% matte tin
plated leadframe).
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
...................................50
V
VREG (Transient) ...............................................15
V
Logic Input Voltage Range, V
IN
...–0.3
V to V
LCAP
+0.3 V
Sense Voltage, V
SENSE
...........................
–5 V to 1.5 V
Pins: SA, SB, SC...................................
–5 V to 50 V
Pins: GHA, GHB, GHC ..................
–5 V to V
BB
+ 17 V
Pins: CA, CB, CC ...........................SA/SB/SC
+ 17 V
Operating Temperature Range
Ambient Temperature, T
A
.............–20°C
to +85°C
Junction Temperature, T
J
............................+150°C
Storage Temperature, T
S
..........–55°C
to +150°C
Thermal Impedance (Typical), at T
A
= +25ºC;
measured on a JEDEC-standard "High-K" PCB
A3938EQ, R
θJA
........................................37°C/W
A3938LD, R
θJA
........................................38°C/W
A3938LQ, R
θJA
........................................44°C/W
26301.104B
Data Sheet
A3938EQ, 32-pin PLCC
A3938LQ, 36-pin QSOP
A3938LD, 38-pin TSSOP
FEATURES
Drives wide range of N-channel MOSFETs
Low-side synchronous rectification
Power MOSFET protection
Adjustable dead time for cross-con-
duction protection
Selectable coast or dynamic brake on
power-down or RESET input
Fast/slow current decay modes
Internal PWM current control
Motor lead short-to-ground
protection
Internal 5 V regulator
Fault diagnostic output
Thermal shutdown
Undervoltage protection
Use the following complete part numbers when ordering:
Part Number
A3938SEQ
A3938SLQ
A3938SLD
A3938SLD-T
Pins
32
36
38
38
Package
PLCC
QSOP
TSSOP
TSSOP, Lead-free
26301.104B
Three-Phase Power MOSFET Controller
Functional Block Diagram
(This diagram shows only one of the three outputs)
A3938
Data Sheet
FAULT
Short to GND
TSD
O.D.
Invalid Hall
VREG Undervoltage
VBB
A
+
VREG
Regulator
+
10 uF
CA
C
BOOT
0.1 uF
0.1 uF
LCAP
+
0.1 uF
H1
Charge Pump
H2
H3
PWM
Control
Logic
High-Side
Protection
Logic
Turn-On
Delay
High-Side
Driver
GHA
To Phase C
DIR
RESET
SA
BRAKE
VREG
MODE
Low-Side
Protection
Logic
RC
C
T
R
T
RC Blanking
Fixed Off-Time
Turn-On
Delay
Low-Side
Driver
GLA
To Phase B
SENSE
R
S
REF
VREG
DEAD
Dead-Time
Adjust
V
REG
UVLO
RESET
AGND
Power Loss
Brake
PGND
BRKCAP
+
4.7uF
BRKSEL
A
For 12 V applications, VBB must be shorted to VREG. For this condition, the absolute
maximum rating of 15 V on VREG must be maintained to prevent damage to the A3938.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
26301.104B
Three-Phase Power MOSFET Controller
ELECTRICAL CHARACTERISTICS
1,2
Unless otherwise noted: T
A
= 25°C, V
BB
= 18 V to 50 V, C
LCAP
= 0.1 µF, C
BOOT
= 0.1 µF,
C
VREG
= 10 µF, PWM = 22.5 kHz, square wave, two phases active
Characteristics
Quiescent Current
LCAP Regulator
VREG =VBB Supply Voltage Range
VREG Output Voltage
VREG Load Regulation
VREG Line Regulation
Control Logic
Logic Input Voltage
V
IN(1)
V
IN(0)
Logic Input Current
Gate Drive
Low-Side Drive, Output High
High-Side Drive, Output High
Pull-Up Switch Resistance
Pull-Down Switch Resistance
Low-Side Switching, 10/90 Rise Time
Low-Side Switching, 10/90 Fall Time
High-Side Switching, 10/90 Rise Time
High-Side Switching, 10/90 Fall Time
Propagation Delay; GHx,GLx Rising
Propagation Delay; GHx,GLx Falling
Dead Time, Maximum
Dead Time, Minimum
V
HGL
V
HGH
R
DS(ON)
R
DS(ON)
tr
GL
tf
GL
tr
GH
tf
GH
T
pr
T
pf
t
DEAD
t
DEAD
I
gx
= 0
I
gx
= 0
I
gx
= –50 mA
I
gx
= 50 mA
C
load
= 3300 pF
C
load
= 3300 pF
C
load
= 3300 pF
C
load
= 3300 pF
PWM to gate drive out, C
load
= 3300 pF
PWM to gate drive out, C
load
= 3300 pF
V
dead
= 0, GHx to GLx, C
load
= 0
I
DEAD
= 780 µA, GLx to GHx, C
load
= 0
V
REG
– 0.8 V
REG
– 0.5
10.4
–
–
–
–
–
–
–
–
3.5
50
11.6
14
4
120
60
120
60
220
110
5.6
100
–
12.8
–
–
–
–
–
–
–
–
7.6
150
V
V
Ω
Ω
ns
ns
ns
ns
ns
ns
µs
ns
I
IN(1)
I
IN(0)
Minimum high level for logical 1
Maximum low level for logical 0
V
IN
= 2.0 V
V
IN
= 0.8 V
2.0
–
–30
–50
–
–
–
–
–
0.8
–90
–130
V
V
µA
µA
Symbol
I
VBB
V
LCAP
V
REG
V
REG
V
REGLOAD
V
REGLIN
Test Conditions
RESET = 1, Coast mode, stopped
I
lcap
= –3.0 mA
VREG = VBB, observe maximum rating = 15 V
V
BB
= 13.2 V to 18 V, I
vreg
= –10 mA
V
BB
= 18 V to 50 V, I
vreg
= –10 mA
I
vreg
= –1 mA to –30 mA, Coast mode
I
vreg
= –10 mA, Coast mode
Min.
–
4.75
10.8
–
12.4
–
–
Typ.
1
–
5
–
V
BB
– 2.5
13
25
40
Max.
8.0
5.25
13.2
–
13.6
–
–
Units
mA
V
V
V
V
mV
mV
A3938
Data Sheet
Continued on next page...
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3
26301.104B
Three-Phase Power MOSFET Controller
A3938
Data Sheet
ELECTRICAL CHARACTERISTICS
1,2
(continued)
Unless otherwise noted: T
A
= 25°C, V
BB
= 18 V to 50 V, C
LCAP
= 0.1 µF,
C
BOOT
= 0.1 µF, C
VREG
= 10 µF, PWM = 22.5 kHz, square wave, two phases active
Characteristics
Bootstrap Capacitor
Bootstrap Capacitor Voltage
Bootstrap R
OUT
Charge Current (Source)
Current Limit Circuitry
Input Offset Voltage
Input Current , Sense pin
Input Current , Reference pin
Blank Time
RC Charge Current
RC Voltage Threshold
Protection Circuitry
Bootstrap Charge Threshold
Short to Ground, Drain-Source Monitor
VREG Undervoltage Threshold
Fault Output Voltage
Brake Capacitor Supply Current
Low Side Gate Voltage
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1
Symbol
Test Conditions
Min.
Typ.
1
Max.
Units
V
CX
R
CX
I
CX
I
cx
= 0, V
sx
= 0, V
reg
= 13 V
I
cx
= –50 mA
10.4
–
100
11.6
9
–
12.8
12
–
V
Ω
mA
V
IO
I
B
I
B
t
BLANK
I
RC
V
RCL
V
RCH
0 V < V
cmr
< 1.5 V
0 V < V
cm
, V
diff
< 1.5 V
0 V < V
cm
, V
diff
< 1.5 V
R = 56 kΩ, C = 470 pF
–
–
–
–
–0.9
1.0
2.7
–
–25
0
0.91
–1
1.1
3.0
±5
–
–
–
–1.1
1.2
3.3
mV
µA
µA
µs
mA
V
V
I
cx
V
dsh
UVLO
V
OUT
I
BRAKE
V
GLBH
T
J
∆T
J
GHx turns on, and GLx turns off, at I
cx
V
BB
– V
SX
, high side on
V
REG
increasing
V
REG
decreasing
I
OL
= 1 mA
V
BB
= 8 V, BRKSEL = 1
V
BB
=0, BRKCAP = 8V
–
1.3
9.2
8.6
–
–
–
–
–
–9
2.0
9.7
9.1
–
30
6.6
165
10
–
2.7
10.2
9.6
0.5
–
–
–
–
mA
V
V
V
V
µA
V
°C
°C
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
2
Negative current is defined as conventional current coming out of (sourced from) the specified device terminal.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
26301.104B
Three-Phase Power MOSFET Controller
Pin Descriptions
RESET.
A logic input that enables the device. Has internal
50 kΩ pull-up to LCAP. Setting RESET to 1 coasts or brakes
the motor, depending on the state of the BRKSEL pin. Set-
ting RESET to 0 enables the gate drive to follow commuta-
tion logic. Setting RESET to 1 overrides the BRAKE pin.
the motor depending on stored setting for BRKSEL).
• Thermal shutdown (coasts the motor).
• Motor lead (SA/SB/SC) connected to ground (turns off
only the high-side power MOSFETs).
Only the “short-to-ground” fault is latched, but it is cleared
at each commutation. If the motor has stalled due to a short-
to-ground being detected, toggling the RESET pin or repeat-
ing a power-up sequence clears the fault.
A3938
Data Sheet
GLA/GLB/GLC.
Low-side gate drive outputs for external
MOSFET drivers. External series gate resistors can be used
to control slew rate seen at the power driver gate, thereby
controlling the
di/dt
and
dv/dt
of Sx outputs.
SA/SB/SC.
Directly connected to the motor terminals,
these pins sense the voltages switched across the load. The
pins are also connected to the negative side of the bootstrap
capacitors and the negative supply connections for the
fl
oat-
ing high-side drivers.
BRAKE.
Logic input for braking function. Setting BRAKE
to 1 turns on low-side MOSFETs, and turns off the high-side
MOSFETs. This effectively shorts the BEMF in the windings
and brakes the motor. Internal 50 kΩ pull-up to LCAP. Set-
ting RESET to 1 overrides this BRAKE pin. See also BRKSEL.
GHA/GHB/GHC.
High-side gate drive outputs for
N-channel MOSFET drivers. External series gate resistors
can be used to control slew rate seen at the power driver
gate, thereby controlling the
di/dt
and
dv/dt
of Sx outputs.
BRKCAP.
This pin is for connection of the reservoir
capacitor used to provide the positive power supply for the
sink drive outputs for a power-down condition. This allows
predictable braking, if desired. Using a 4.7
µF
capacitor will
provide 6.5 V gate drive for 300 ms. If the power-down brak-
ing option is not needed (i.e., BRKSEL = 0), then this pin
should be tied to VREG.
CA/CB/CC.
High-side connections for bootstrap capaci-
tors, providing positive supply for high-side gate drivers. The
bootstrap capacitors are charged to approximately VREG
when the output Sx terminals go low. When the outputs
swing high, the voltages on these pins rise with the outputs to
provide the boosted gate voltages needed for the N-channel
power MOSFETs.
MODE.
Logic input to set current-decay mode. In response
to a PWM Off command, Slow Decay mode (MODE = 1)
switches off the high-side FET, and Fast Decay mode
(MODE = 0) switches off the high-side and low-side FETs.
Has an internal 50 kΩ pull-up to LCAP.
BRKSEL
.
Logic input to enable/disable braking upon
power-down condition or RESET = 1. Internal 50 kΩ pull-up
to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting
BRKSEL to 1 enables Brake mode.
PWM.
Speed control input. Setting PWM to 1 turns on
MOSFETs selected by Hall input logic. Setting PWM to 0
turns off the selected MOSFETs. Keep the PWM input held
high to utilize internal current control circuitry. Internal
50 kΩ pull-up to LCAP.
H1/H2/H3.
Hall sensor inputs with internal, 50 kΩ pull-ups
to LCAP. Configured for 120-degree electrical spacing.
RC.
Analog input. Connection for R
T
and C
T
to set the
DIR.
Logic input to reverse rotation (see the table Commu-
tation Truth Table, on the next page). Has internal, 50 kΩ
pull-up to LCAP.
fi
xed off-time. C
T
also sets the BLANK time (see the section
Application Information). It is recommended that the
fi
xed
off-time should not be less than 10 µs. The resistor should be
in the range between 10 kΩ and 500 kΩ.
VREG.
Regulated 13 V supply for the low-side gate drive
and the bootstrap capacitor charge circuit. As a regulator, use
a 10 µF decoupling/storage capacitor (ESR < 1
Ω)
from this
pin to AGND, as close to the device pins as possible.
Note: For 12 V applications, the VREG pin should be
shorted to VBB.
FAULT.
Open-drain output to indicate fault condition. Will
be pulled high (usually by 5.1 kΩ external pull-up) for any of
the following fault conditions:
• Invalid Hall sensor input code (coasts the motor).
• Undervoltage condition detected at VREG (coasts or brakes
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
