INTEGRATED CIRCUITS
DATA SHEET
SAA7184; SAA7185B
Digital Video Encoders
(DENC2-M6)
Preliminary specification
Supersedes data of 1995 Nov 14
File under Integrated Circuits, IC22
1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
FEATURES
•
CMOS 5 V device
•
Digital PAL/NTSC encoder
•
System pixel frequency 13.5 MHz
•
Accepts MPEG decoded data
•
8-bit wide MPEG port
•
Input data format Cb, Y, Cr etc. (CCIR 656)
•
16-bit wide YUV input port
•
I
2
C-bus control port or alternatively MPU parallel control
port
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
OVL overlay with Look-Up Tables (LUTs) 8
×
3 bytes
•
Colour bar generator
•
Line 21 closed caption encoder
•
Cross-colour reduction
•
Macrovision revision_6 Pay-per-View copy protection
system as option (SAA7184 only).
Remark:
This device
is protected by U.S. patent numbers 4631603 4577216
and 4819098 and other intellectual property rights.
Use of the Macrovision anticopy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
•
DACs operating at 27 MHz with 10-bit resolution
•
Controlled rise and fall times of output syncs and
blanking
•
Down-mode of DACs
•
CVBS and S-Video output simultaneously
•
PLCC68 package.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7184WP
SAA7185BWP
PLCC68
DESCRIPTION
plastic leaded chip carrier; 68 leads
SAA7184; SAA7185B
GENERAL DESCRIPTION
The SAA7184 and SAA7185B digital video encoders 2
(DENC2-M6) encode digital YUV video data to an NTSC
or PAL CVBS or S-Video signal.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. The device includes a
sync/clock generator and on-chip Digital-to-Analog
Converters (DACs).
The circuit is compatible to the DIG-TV2 chip family.
VERSION
SOT188-2
1996 Jul 03
2
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
ILE
DLE
T
amb
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C and CVBS without load
−
(peak-to-peak value)
load resistance
LF integral linearity error
LF differential linearity error
operating ambient temperature
80
−
−
0
PARAMETER
SAA7184; SAA7185B
MIN.
4.75
4.5
−
−
TYP.
5.0
5.0
50
130
2
−
−
−
−
MAX.
5.25
5.5
55
170
−
−
±2
±1
+70
V
V
UNIT
mA
mA
V
V
Ω
LSB
LSB
°C
TTL compatible
BLOCK DIAGRAM
KEY
SEL_ED
18
MP7
to MP0
VP0
to VP7
20 to 27
8
9 to 16
8
OVL0
to OVL2
32 to 34
VDDD1
RTCI
43
to VDDD3
17,37,67
VDDA1
to
VrefH VDDA4
IOA
47 55 48,50,
54,56
53
A
51
D
49
52
46
31
DATA
MANAGER
ENCODER
OUTPUT
INTERFACE
CVBS
Y
CHROMA
VSSA
VrefL
8
8
internal control bus
8
RCM1
RCM2
29
8
30
8
clock timing signals
8
SAA7184
SAA7185B
CONTROL
INTERFACE
SYNC
CLK
1,8,19
28,35,
42,62
63 to 66
2 to 5
68
61
59
60
58
57
41
XTALI
40
38
LLC
39
36
6
7
MGC679
VSSD1
to
VSSD7
DP0
to DP7
CSN/SA
A0/SDA
RES
CDIR
RCV2
SEL_MPU
RWN/SCL
DTACK
XTALO
CREF
RCV1
Fig.1 Block diagram.
1996 Jul 03
ll pagewidth
3
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
PINNING
SYMBOL
V
SSD1
DP4 to DP7
PIN
1
2 to 5
I/O
−
I/O
digital ground 1
SAA7184; SAA7185B
DESCRIPTION
Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
Raster control 1 for video port; depending on the synchronization mode, this
pin receives or provides a VS/FS/FSEQ signal.
Raster control 2 for video port; depending on the synchronization mode, this
pin receives or provides an HS/HREF/CBL signal.
digital ground 2
Video port; this is an input for CCIR 656 compatible multiplexed video data. If
the 16-bit DIG-TV2 format is used, then Y data is input.
digital supply voltage 1
select encoder data; selects input data either from the MPEG port or from
the video port
digital ground 3
MPEG port; it is an input for CCIR 656 style multiplexed YUV data.
digital ground 4
Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal.
Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG
decoder.
key signal for OVL (active HIGH)
on-screen display data; this is the index for the internal OVL look-up tables
digital ground 5
Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal,
if not LLC and CREF are generated by the internal crystal oscillator.
digital supply voltage 2
Line-locked clock; this is the 27 MHz master clock for the encoder. The
direction is set by the CDIR pin.
Clock reference signal; this is the clock qualifier for DIG-TV2 compatible
signals. The polarity is programmable by software.
crystal oscillator output (to crystal)
Crystal oscillator input (from crystal). If the oscillator is not used, this pin
should be connected to ground.
digital ground 6
Real time control Input; if the clock is provided by the SAA7151B or
SAA7111, RTCI should be connected to the RTCO pin of the decoder to
improve the signal quality.
test pin (should be connected to digital ground for normal operation)
test pin (should be connected to digital ground for normal operation)
lower reference voltage input for the DACs
upper reference voltage input for the DACs
analog positive supply voltage 1 for the DACs and output amplifiers
RCV1
RCV2
V
SSD2
VP0 to VP7
V
DDD1
SEL_ED
V
SSD3
MP7 to MP0
V
SSD4
RCM1
RCM2
KEY
OVL0 to OVL2
V
SSD5
CDIR
V
DDD2
LLC
CREF
XTALO
XTALI
V
SSD6
RTCI
6
7
8
9 to 16
17
18
19
20 to 27
28
29
30
31
32 to 34
35
36
37
38
39
40
41
42
43
I/O
I/O
−
I
I
I
−
I
−
O
O
I
I
−
I
I
I/O
I/O
O
I
−
I
AP
SP
V
refL
V
refH
V
DDA1
44
45
46
47
48
−
−
I
I
I
1996 Jul 03
4
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SYMBOL
CHROMA
V
DDA2
Y
V
SSA
CVBS
V
DDA3
IOA
V
DDA4
RES
DTACK
RWN/SCL
A0/SDA
CSN/SA
PIN
49
50
51
52
53
54
55
56
57
58
59
60
61
I/O
O
I
O
−
O
I
I
I
I
O
I
I/O
I
DESCRIPTION
analog output of the chrominance signal
analog supply voltage 2 for the DACs and output amplifiers
analog output of the luminance signal
analog ground for the DACs and output amplifiers
analog output of the CVBS signal
analog supply voltage 3 for the DACs and output amplifiers
current input for the output amplifiers (connected via a 15 kΩ resistor to
V
DDA
)
analog supply voltage 4 for the DACs and output amplifiers
Reset input, active LOW. After reset is applied, all outputs are in 3-state input
mode. The I
2
C-bus receiver waits for the start condition.
Data acknowledge output of the parallel MPU interface, active LOW,
otherwise high impedance.
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU
interface. Otherwise it is the I
2
C-bus serial clock input.
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU
interface. Otherwise it is the I
2
C-bus serial data input/output.
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel
MPU interface. Otherwise it is the I
2
C-bus slave address select pin. When
LOW slave address = 88H, when HIGH slave address = 8CH.
digital ground 7
Lower 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
digital supply voltage 3
Select MPU interface input; if it is HIGH, the parallel MPU interface is active,
if not the I
2
C-bus interface will be used.
V
SSD7
DP0 to DP3
62
63 to 66
−
I/O
V
DDD3
SEL_MPU
67
68
I
I
1996 Jul 03
5
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