ACT–S512K32 High Speed
16 Megabit SRAM Multichip Module
Features
■
4 Low Power CMOS 512K x 8 SRAMs in one MCM
■
Factory configured as 512K x 32; User configurable as 1M x 16 or 2M x 8
■
Input and Output TTL & CMOS Compatible Design
■
Fast 17,20,25,35,45,55ns Access Times
■
Full Commercial, Industrial and Military (-55°C to +125°C)
CIRCUIT TECHNOLOGY
www.aeroflex.com
General Description
The ACT–S512K32 is a High
Speed, 16 megabit CMOS
SRAM
Multichip
Module
(MCM) designed for full
temperature range industrial,
military, or space, mass
memory and fast cache
applications.
The MCM can be organized
as a 512K x 32 bit, 1M x 16 bit
or 2M x 8 bit device and is
input
and
output
TTL
compatible. Writing is executed
when the write enable (WE)
and chip enable (CE) inputs
are low and output enable (OE)
input is high. Reading is
accomplished when WE is high
and CE and OE are both low.
Access time grades of 17ns,
20ns, 25ns, 35ns, 45ns and
55ns maximum are standard
high speed versions.
The +5 Volt power supply
version is standard and +3.3
Volt lower power model is a
future optional product.
The products are designed
for
operation
over
the
temperature range of -55°C to
+125°C and under the full
military environment. DESC
Standard Military Drawing
(SMD) numbers are released.
The
ACT-S512K32
is
manufactured in Aeroflex’s
80,000
square
foot
MIL-PRF-38534
certified
facility in Plainview, N.Y.
Temperature Range
■
MIL-PRF-38534 Compliant MCMs Available
■
+5 V Power Supply
■
Available in two Surface Mount Packages, and two PGA Type Package
●
●
68–Lead, Low Profile CQFP(F1), 1.56"SQ x .140"max
68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max
(.18 max thickness available, contact factory for details)
(Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)
●
68–Lead, Single-Cavity CQFP (F18), .94"SQ x .140"max
(Drops into the 68
Lead JEDEC .99"SQ CQFJ footprint)
●
66 Pin, 1.38" x 1.38" x .245" PGA Type, Aeroflex code# "P1"
●
66 Pin, 1.09" x 1.09" x .185" PGA Type, With Shoulder, Aeroflex code# "P7"
■
Internal Decoupling Capacitors
■
DESC SMD# 5962–94611 Released (F1,F2,F18,P1,P7)
Block Diagram – PGA Type Package (P1,P7) & CQFP (F2,F18)
Pin Description
WE
1
CE
1
WE
2
CE
2
WE
3
CE
3
WE
4
CE
4
I/O
0-31
A
0
– A
18
OE
512Kx8
512Kx8
512Kx8
512Kx8
A
0–18
WE
1–4
CE
1–4
OE
V
cc
8
I/O
0-7
8
I/O
8-15
8
I/O
16-23
8
I/O
24-31
GND
NC
Data I/O
Address Inputs
Write Enables
Chip Enables
Output Enable
Power Supply
Ground
Not Connected
Block Diagram – CQFP(F1)
Pin Description
CE
1
WE
OE
A
0
– A
18
512Kx8
512Kx8
512Kx8
512Kx8
CE
2
CE
3
CE
4
I/O
0-31
A
0–18
WE
CE
1–4
OE
V
cc
8
I/O
0-7
8
I/O
8-15
8
I/
O
16-23
8
I/O
24-31
GND
NC
Data I/O
Address Inputs
Write Enable
Chip Enables
Output Enable
Power Supply
Ground
Not Connected
eroflex Circuit Technology - Advanced Multichip Modules © SCD1660 REV D 5/21/01
Absolute Maximum Ratings
Symbol
Tc
T
STG
P
D
Ø
J-C
V
G
T
L
Operating Temperature
Storage Temperature
Maximum Package Power Dissipation
Hottest Die, Max Thermal Resistance - Junction to Case
Maximum Signal Voltage to Ground
Maximum Lead Temperature (10 seconds)
Rating
Range
-55 to +125
-65 to +150
3.0
5
-0.5 to +7
300
Units
°C
°C
W
°C/W
V
°C
Normal Operating Conditions
Symbol
V
CC
V
IH
V
IL
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Minimum
+4.5
+2.2
-0.5
Maximum
+5.5
V
CC
+ 0.3
+0.8
Units
V
V
V
Capacitance
(V
IN
= 0V, f = 1MHz, Tc = 25°C
)
Symbol Parameter
C
AD
C
OE
C
WE
C
CE
C
I
/
O
A
0
–
A
18
Capacitance
OE Capacitance
CQFP (F1) Package
PGA (P1 & P7) and CQFP (F2 & F18) Packages
Chip Enable Capacitance
I/O
0
– I/O
31
Capacitance
Maximum
50
50
50
20
20
20
Units
pF
pF
pF
pF
pF
pF
This parameter is guaranteed by design but not tested
DC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, Tc = -55°C to +125°C, unless otherwise indicated)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current 32 Bit Mode
Standby Current
Operating Supply Current 32 Bit Mode
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC1
x32
I
SB1
I
CC2
x32
I
SB2
V
OL
V
OH
Conditions
V
CC
= +5.5V, V
IN
= 0 or V
CC
CE = V
IH
, OE = V
IH
, V
OUT
= 0 to V
CC
CE = V
IL
, OE = V
IH
, V
CC
= +5.5V
f = 5 MHz CMOS Compatible
CE = V
CC
, OE = V
IH
, V
CC
= +5.5V
f = 5 MHz CMOS Compatible
CE = V
IL
, OE = V
IH
, V
CC
= +5.5V
f = 50 MHz CMOS Compatible
CE = V
CC
, OE = V
IH
, V
CC
= +5.5V
f = 50 MHz CMOS Compatible
I
OL
= 8 mA, V
CC
= +4.5V
I
OH
= -4.0 mA, V
CC
= +4.5V
2
ALL Speeds
Min
Max
-
-
-
-
-
-
-
2.4
10
10
600
80
700
280
0.4
-
Units
µA
µA
mA
mA
mA
mA
V
V
Aeroflex Circuit Technology
SCD1660 REV D 5/21/01 Plainview NY (516) 694-6700
AC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, Tc = -55°C to +125°C)
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Output Enable to Output Valid
Chip Enable to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z
*
Sym
t
RC
t
AA
t
ACE
t
OH
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
–017
–020
–025
–035
–045
–055
Units
Min Max Min Max Min Max Min Max Min Max Min Max
17
-
-
0
-
2
0
-
-
-
17
17
-
9
-
-
12
12
20
-
-
0
-
2
0
-
-
12
12
10
-
20
20
25
-
-
0
-
2
0
-
-
25
25
-
12
-
-
12
12
4
0
-
-
15
15
35
-
-
0
25
-
35
35
45
-
-
0
-
4
0
-
-
-
45
45
-
25
-
-
20
20
4
0
-
-
55
-
-
0
-
55
55
-
25
-
-
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Parameters guaranteed by design but not tested
Write Cycle
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
Sym
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
OW
t
WHZ
t
DH
t
AH
–017
–020
–025
–035
–045
–055
Units
Min Max Min Max Min Max Min Max Min Max Min Max
17
15
15
11
15
2
2
-
0
0
-
-
-
-
-
-
-
9
-
-
0
0
20
15
15
12
15
2
3
-
-
-
-
-
-
-
11
-
-
0
0
25
17
17
13
17
2
4
-
-
-
-
-
-
-
13
-
-
0
0
35
25
25
20
25
2
4
-
-
-
-
-
-
-
15
-
-
0
5
45
35
35
25
35
2
5
-
-
-
-
-
-
-
20
-
-
55
50
50
25
40
2
5
-
0
5
-
-
-
-
-
-
-
20
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Parameters guaranteed by design but not tested
Data Retention Electrical Characteristics (Special Order Only)
(Tc = -55°C to +125°C)
Parameter
V
CC
for Data Retention
Data Retention Current
Sym
V
DR
I
CCDR1
Test Conditions
CE
≥
V
CC
– 0.2V
V
CC
= 3V
All Speeds
Min
Max
2
-
5.5
28
Units
V
mA
Truth Table
Mode
Standby
Read
Output Disable
Write
Aeroflex Circuit Technology
CE
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
Data I/O
High Z
Data Out
High Z
Data In
3
Power
Standby (deselect/power down)
Active
Active (deselected)
Active
SCD1660 REV D 5/21/01 Plainview NY (516) 694-6700
Timing Diagrams
Read Cycle Timing Diagrams
Read Cycle 1 (CE = OE = V
IL
, WE = V
IH
)
t
RC
A
0-18
t
AA
t
OH
D
I/O
Previous Data Valid
Data Valid
CE
t
AS
WE
S
EE
N
OTE
Write Cycle Timing Diagrams
Write Cycle 1 (WE Controlled, OE = V
IL
)
t
WC
A
0-16
t
AW
t
CW
t
AH
t
WP
S
EE
N
OTE
t
OW
t
WHZ
t
DW
Data Valid
t
DH
D
I/O
Read Cycle 2 (WE = V
IH
)
t
RC
A
0-18
t
AA
CE
t
ACS
t
CLZ
S
EE
N
OTE
Write Cycle 2 (CE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CHZ
S
EE
N
OTE
t
AH
t
CW
t
AS
CE
OE
t
WP
t
OE
t
OLZ
S
EE
N
OTE
t
OHZ
S
EE
N
OTE
WE
t
DW
t
DH
D
I/O
High Z
Data Valid
D
I/O
Data Valid
UNDEFINED
DON’T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source
I
OL
Parameter
Input Pulse Level
To Device Under Test
C
L
=
50 pF
I
OH
Current Source
V
Z
~ 1.5 V (Bipolar Supply)
Typical
0 – 3.0
5
1.5
Units
V
ns
V
Input Rise and Fall
Input and Output Timing Reference
Level
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75Ω.
4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
4
SCD1660 REV D 5/21/01 Plainview NY (516) 694-6700
Pin Numbers & Functions
66 Pins — PGA-Type
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Function
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
WE
2
CE
2
GND
I/O
11
A
10
A
11
Pin #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
A
12
Vcc
CE
1
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
Pin #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Function
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
V
CC
CE
4
WE
4
I/O
27
A
3
A
4
A
5
Pin #
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Function
WE
3
CE
3
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
Package Outline — PGA-Type "P1"
Package Outline — PGA-Type "P7
Bottom View (P1)
Side View
(P1)
.245
MAX
.025
.035
1.400 SQ
MAX
1.000
TYP
.600
TYP
Bottom View (P7)
Side View
(P7)
.185
MAX
Pin 1
.025
.035
Pin 56
.050 DIA
TYP
1.000
TYP
1.000
TYP
1.085 SQ
MAX
1.000
TYP
.600
TYP
Pin 1
.050 DIA
TYP
Pin 56
Limited Availability
Use ''P7'' package for new designs
.100 TYP
.020
.016
Pin 66
.100
TYP
.020
.016
Pin 66
Pin 11
.145
MIN
.100
TYP
.145
MIN
.100 TYP
Pin 11
All dimensions in inches
Aeroflex Circuit Technology
5
SCD1660 REV D 5/21/01 Plainview NY (516) 694-6700
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