SEMICONDUCTOR
SYNERGY
3.3V 1:4 CLOCK
DISTRIBUTION IC
DESCRIPTION
ClockWorks™
SY100EL15L
ClockWorks™
SY100EL15L
FEATURES
s
s
s
s
s
s
3.3V power supply
50ps output-to-output skew
Low power
Synchronous enable/disable
Multiplexed clock input
75K
Ω
internal input pull-down resistors
s
ESD protection of 2000V
s
Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
V
CC
16
EN SCLK CLK CLK V
BB
15
14
13
1
D
Q
0
12
11
SEL V
EE
10
9
1
Q
0
2
Q
0
3
Q
1
4
Q
1
5
Q
2
6
Q
2
7
Q
3
8
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to V
EE
and CLK input will bias around
V
CC
/2.
Q
3
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
SCLK
EN
SEL
V
BB
Q
0-3
Function
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TRUTH TABLE
CLK
L
H
X
X
X
SCLK
X
X
L
H
X
SEL
L
L
H
H
X
EN
L
L
L
L
H
Q
L
H
L
H
L*
* On next negative transition of CLK or SCLK
© 1999 Micrel-Synergy
Rev.: A
Amendment: /0
5-1
Issue Date: December 1999
SEMICONDUCTOR
SYNERGY
ClockWorks™
SY100EL15L
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
EE
V
I
I
OUT
Power Supply (V
CC
= 0V)
Input Voltage (V
CC
= 0V)
Output Current
–Continuous
–Surge
T
A
Operating Temperature Range
50
100
–40 to +85
mA
°C
Rating
Value
–8.0 to 0
0 to –6.0
Unit
VDC
VDC
NOTES:
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at:
3 volt Power Supply Range 100EL15L Series
–3.0V to –3.8V.
DC ELECTRICAL CHARACTERISTICS
V
EE
= 3.3V
±10%;
V
CC
= GND
(1)
T
A
= –40
°
C
Symbol
V
OH
V
OL
V
OHA
V
OLA
V
IH
V
IL
I
IH
I
IL
I
EE
V
BB
Parameter
Output HIGH Voltage
(2)
Output LOW Voltage
(2)
Output HIGH Voltage
(3)
Output LOW Voltage
(3)
Input HIGH Voltage
Input LOW Voltage
Input High Current
Input LOW Current
(4)
CLK
Power Supply Current
Output Reference Voltage
Min.
–1085
–1830
–1095
—
–1165
–1810
—
0.5
–300
—
–1.38
Max.
–880
–1555
—
–1555
–880
–1475
150
—
—
35
–1.26
T
A
= 0
°
C
Min.
–1025
–1810
–1035
—
–1165
–1810
—
0.5
–300
—
–1.38
Max.
–880
–1620
—
–1610
–880
–1475
150
—
—
35
–1.26
Min.
–1025
–1810
–1035
—
–1165
–1810
—
0.5
–300
—
–1.38
T
A
= +25
°
C
Typ.
–955
–1705
—
—
—
—
—
—
25
—
Max.
–880
–1620
—
–1610
–880
–1475
150
—
—
35
–1.26
T
A
= +85
°
C
Min.
–1025
–1810
–1035
—
–1165
–1810
—
0.5
–300
—
–1.38
Max.
–880
–1620
—
–1610
–880
–1475
150
—
—
38
–1.26
Unit
mV
mV
mV
mV
mV
mV
µA
µA
mA
V
NOTES:
1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50Ω resistor to –2.0V.
2. V
IN
= V
IH
(Max) or V
IL
(Min).
3. V
IN
= V
IH
(Min) or V
IL
(Max).
4. V
IN
= V
IL
(Max).
5-2
SEMICONDUCTOR
SYNERGY
ClockWorks™
SY100EL15L
AC ELECTRICAL CHARACTERISTICS
V
EE
= 3.3V
±10%;
V
CC
= GND
(1)
T
A
= –40
°
C
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
Part-to-Part Skew
(1)
Within-Device Skew
Setup Time EN
Hold Time EN
Minimum Input Swing
CLK
Common Mode Range
(2)
V
PP
< 500mV
V
PP
≥
500mV
Output Rise/Fall TimesQ
(20% – 80%)
Min.
460
410
410
—
—
150
400
250
–2.0
–1.8
375
Max.
660
710
710
200
50
—
—
—
–0.4
–0.4
625
T
A
= 0
°
C
Min.
470
420
420
—
—
150
400
250
–2.1
–1.9
325
Max.
670
720
720
200
50
—
—
—
–0.4
–0.4
575
Min.
470
420
420
—
—
150
400
250
–2.1
–1.9
325
T
A
= +25
°
C
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
670
720
720
200
50
—
—
—
–0.4
–0.4
575
T
A
= +85
°
C
Min.
500
450
470
—
—
150
400
250
–2.1
–1.9
325
Max.
700
750
750
200
50
—
—
—
–0.4
–0.4
575
ps
ps
ps
ps
mV
mV
Unit
ps
t
skew
t
S
t
H
V
PP
V
CMR
t
r
t
f
NOTES:
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. V
CMR
is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the V
CMR
range
and the input swing is greater than V
PP
(Min.) and <1V. The lower end of the V
CMR
range varies 1:1 with V
EE
. The numbers in the spec table assume a
nominal V
EE
= –3.3V. Note for PECL operation, the V
CMR
(Min) will be fixed at 3.3V – |V
CMR
(Min)|.
PRODUCT ORDERING CODE
Ordering
Code
SY100EL15LZC
SY100EL15LZCTR
Package
Type
Z16-2
Z16-2
Operating
Range
Commercial
Commercial
5-3
SEMICONDUCTOR
SYNERGY
ClockWorks™
SY100EL15L
16 LEAD PLASTIC SOIC .150" WIDE (Z16-2)
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
+ 1 (408) 914-7878
WEB
+ 1 (408) 980-9191
FAX
http://www.synergysemi.com http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 1999 Micrel Incorporated
5-4
微控制器 MCU
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