INTEGRATED CIRCUITS
DATA SHEET
SAA4700
VPS dataline processor
Preliminary specification
File under Integrated Circuits, IC02
March 1991
Philips Semiconductors
Preliminary specification
VPS dataline processor
FEATURES
•
Adaptive sync slicer with buffered
composite sync output VCS
•
Adaptive data slicer
•
Data rate clock regenerator
•
Field selection and line 16
decoding
•
Startcode and biphase check
•
Data valid output
•
Storage of data line information in a
40 bit register bank
•
I
2
C-bus
transmission
QUICK REFERENCE DATA
SYMBOL
V
P
I
P
V
i CVBS
PARAMETER
supply voltage (pins 15 and
16)
total supply current
CVBS input signal
sync-to-white
(peak-to-peak value)
operating ambient
temperature
MIN.
4.5
−
TYP.
5
18
SAA4700
MAX.
5.5
23
UNIT
V
mA
GENERAL DESCRIPTION
The SAA4700 is a bipolar integrated
circuit designed for use in dataline
receivers and incorporates a dataline
slicer and decoder. The slicer extracts
the dataline signal from the video
signal and regenerates the data
clock. It also provides signals for the
decoder in order to decode the binary
data that is transmitted in line 16 of
every first field of the composite video
signal (video programming signal and
video recording programming by
Teletext, VPS and VPT systems).
The decoded information out of words
5 and 11 to 14 is accessed via the
built-in I
2
C-bus interface. This
information then can be used for
programming a video cassette
recorder in order to start and stop a
recording of a television program at
the correct aligned time, regardless of
a delay or extension in the
transmission time of the required
program.
T
amb
0.5
0
1
−
1.4
+70
V
°C
ORDERING AND PACKAGE INFORMATION
EXTENDED TYPE
NUMBER
SAA4700
Note
1. SOT102-1; 1996 December 4.
PACKAGE
PINS
18
PIN POSITION
DIL
MATERIAL
plastic
CODE
SOT102
(1)
March 1991
2
Philips Semiconductors
Preliminary specification
VPS dataline processor
SAA4700
handbook, full pagewidth
CSO
0.1
µF
5
6
(test line 16)
11
FIELD SELECTOR
LINE 16 DECODER
line 16
DAV
AD = LOW
12
OUTPUT
CONTROLLER
7
8
I
2
C-BUS
CONTROL
SCL
SDA
CVBS
4.7 nF
2
SYNC
SEPARATOR
9
470 pF
SAA4700
1 nF
5
8
1
DATA
SLICER
data
40-BIT DATA
REGISTER
data
4
4.7
kΩ
INPUT
CONTROLLER
40-BIT
DATA LATCH
CLOCK
REGENERATOR
75 kΩ
(2%)
to VP
4.7 nF
22
nF
8.2 kΩ
VCS
13
PLL WITH
5 MHz VCO AND
PHASE DETECTOR
6
MULTIPLEXER
18
REFERENCE
VOLTAGES
POWER-ON RESET
3
4
15
16
external
reset
n.c.
17
TIME BASE
14
10
clock pulse
0.1
µF
+5
V
VP
MEH095
Fig.1 Block diagram and test circuit.
FUNCTIONAL DESCRIPTION
Dataline 16
The information in dataline 16
consists of fifteen 8-bit words; the
total information content is shown in
Table 1; and the organization of
transmitted bytes is shown in Table 2.
Out of the fifteen possible 8-bit words
the SAA4700 extracts words 5 and 11
to 14. The contents of these words
can be read via the built-in I
2
C-bus
interface. The circuit is fully
transparent, thus each bit is
transferred without modification with
only the sequence of words being
changed. Words 11 to 14
are transmitted first followed by
word 5.
By evaluating the sliced sync signal
the circuit can identify the beginning
of dataline 16 in the first field. The
dataline decoder stage releases the
start code detector. When a correct
start code is detected (for timing of
start code detection see Fig.3) words
5 and 11 to 14 are decoded, checked
for biphase errors and stored in a
register bank. If no biphase error has
occurred, the contents of the register
bank are transferred to a second
register bank by the data valid control
signal. If the system has been
addressed, this transfer will be
delayed until the next start or stop
condition of the I
2
C-bus has been
received.
The last bit of correct information on
the dataline remains available until it
is read via the I
2
C-bus. Once the
stored information has been read it is
considered to be no longer valid and
the internal new data flag is reset.
Subsequently, if the circuit is
addressed, the only VPS data that will
be sent back is ”FFF to F”. The same
conditions apply after power-up when
no data can be read out. New data is
available after reception of another
error-free dataline 16.
March 1991
3
Philips Semiconductors
Preliminary specification
VPS dataline processor
PINNING
SYMBOL
CVBS
SYNC
GND1
GND2
C
black
CSO
AD
SCL
SDA
RS
TP
DAV
R
osc
CP
V
P1
V
P2
C
ph
n.c.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DESCRIPTION
video signal input (CVBS from TV)
sync amplitude input (CVBS from TV)
analog ground (0 V)
digital ground (0 V)
capacitor for black level
composite sync output
address set input
I
2
C-bus clock line
I
2
C-bus data line
reset input active LOW
test point for line 16 decoder
data available output active LOW
oscillator resistor for frequency
adjustment
test point clock pulse
+5
V supply voltage (digital part)
+5
V supply voltage (analog part)
capacitor of phase detector
not connected
To enable proper storage of the sync
value in the decoupling capacitor, the
sync generator output resistance
should not exceed 1 kΩ.
Black level
The capacitor connected to pin 5
stores the black level value for the
adaptive sync slicer.
Composite sync output (CSO)
A composite sync output signal for
customer application is provided
(pin 6).
DAV output
The data available output pin 12 is set
LOW after an error free dataline 16 is
received. DAV returnes to HIGH after
the beginning of the next first field. If
Fig.2 Pin configuration
handbook, halfpage
SAA4700
PIN CONFIGURATION
CVBS
SYNC
GND1
GND2
Cblack
CSO
AD
SCL
SDA
1
2
3
4
5
6
7
8
9
MBH796
18 n.c.
17 Cph
16 VP2
15 VP1
SAA4700
14 CP
13 Rosc
12 DAV
11 TP
10 RS
External reset
The circuit provides an internal
power-on reset. When using this
facility pin 10 should be connected to
V
P
or, if external reset
(RESET = LOW) is to be used pin 10
should be prepared by connecting pin
10 via a 10 kΩ pull-up resistor to V
P
.
Reset forces the following:
-
I
2
C-bus
not to acknowledge
no valid data is available DAV
remains HIGH. A short duration pulse
of 1
µs
(Fig.5) is inserted at the
beginning of dataline 16; it will ensure
that a HIGH-to-LOW transmission
occurs which can then be used for
triggering.
5 MHz VCO and phase detector
The resistor connected between pin
13 and V
P2
determines the current
into the voltage controlled oscillator.
The RC network connected to pin 17
acts as a low-pass filter for the phase
detector.
Power supply
To prevent crosscoupling the circuit is
provided with separate ground and
supply pins for analog and digital
parts (pins 3, 4, 15 and 16).
- DAV output to go HIGH (pin 12)
- I
2
C-bus transfer register to “FFF”
CVBS input
The CVBS signal is applied to the
sync separator (pin 2) via a
decoupling capacitor and to the data
slicer (pin 1) via an RC high-pass
filter.
March 1991
4
Philips Semiconductors
Preliminary specification
VPS dataline processor
Table 1
Information per word in dataline 16
content
run in
start code
program source identification (binary coded)
program source identification (ASCII sequential)
sound and VTR control information
program/test picture identification
internal information exchange
address assignment of signal distribution
address assignment of signal distribution
messages/commands
SAA4700
word number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 2
VTR control / information
reserve
VTR control information of dataline 16
VTR CONTROL INFORMATION
Word
number
1
Bit number
Label binary
Word 5:
5
8
0
11
7 8
12
15
16
13
23
24
14
31
XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX
Progr.
source
AD
(1)
Day
Month
Hour
Minute
Nation
Bit1
0
0
System
status code
1
1
Bit3
Pause
code
Interrupt
code
Note
1
0
Bit2 Status
0
1
0
1
2-channel
Mono
Stereo
2-channel
1X00000111111111111111
NC..
.NC
PC...PC
Special system code
Bit4 Status
0
1
free
free
1X00000111111110111111
NC..
.NC
NC..
.NC
PC...PC
1X00000111111101111111
PC...PC
1. address range; NC = nation code; PC = program source code; X = 0 or 1 (bit)
March 1991
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
