MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MJW16212/D
MJF18002 (See MJE18002)
MJF18004 (See MJE18004)
MJF18006 (See MJE18006)
SCANSWITCH
™
NPN Bipolar Power Deflection Transistor
For High and Very High Resolution Monitors
The MJW16212 is a state–of–the–art SWITCHMODE™ bipolar power transistor. It
is specifically designed for use in horizontal deflection circuits for 20 mm diameter
neck, high and very high resolution, full page, monochrome monitors.
•
•
•
•
1500 Volt Collector–Emitter Breakdown Capability
Typical Dynamic Desaturation Specified (New Turn–Off Characteristic)
Application Specific State–of–the–Art Die Design
Fast Switching:
200 ns Inductive Fall Time (Typ)
2000 ns Inductive Storage Time (Typ)
•
Low Saturation Voltage:
0.15 Volts at 5.5 Amps Collector Current and 2.5 A Base Drive
•
Low Collector–Emitter Leakage Current — 250
µA
Max at 1500 Volts — VCES
•
High Emitter–Base Breakdown Capability For High Voltage Off Drive Circuits —
8.0 Volts (Min)
MJF18008 (See MJE18008)
MJW16212*
*Motorola Preferred Device
POWER TRANSISTOR
10 AMPERES
1500 VOLTS – VCES
50 AND 150 WATTS
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MAXIMUM RATINGS
Rating
Symbol
VCES
Value
1500
650
8.0
—
—
Unit
Vdc
Vdc
Vdc
V
Collector–Emitter Breakdown Voltage
Collector–Emitter Sustaining Voltage
Emitter–Base Voltage
VCEO(sus)
VEBO
RMS Isolation Voltage (2)
(for 1 sec, TA = 25
_
C,
Rel. Humidity < 30%)
VISOL
Per Fig. 14
Per Fig. 15
Collector Current — Continuous
Collector Current
— Pulsed (1)
Base Current — Continuous
Base Current
— Pulsed (1)
IC
ICM
IB
IBM
10
15
Adc
Adc
mJ
5.0
10
0.2
Maximum Repetitive Emitter–Base
Avalanche Energy
W (BER)
PD
Total Power Dissipation @ TC = 25
_
C
Total Power Dissipation
@ TC = 100
_
C
Derated above TC = 25
_
C
150
39
1.49
Watts
W/
_
C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 125
CASE 340K–01
TO–247AE
_
C
THERMAL CHARACTERISTICS
Characteristic
Symbol
R
θJC
TL
Max
Unit
Thermal Resistance — Junction to Case
0.67
275
_
C/W
_
C
Lead Temperature for Soldering Purposes
1/8″ from the case for 5 seconds
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle
10%.
(2) Proper strike and creepage distance must be provided.
v
Preferred
devices are Motorola recommended choices for future use and best overall value.
SCANSWITCH and SWITCHMODE are trademarks of Motorola Inc.
REV 2
©
Motorola, Inc. 1996
Motorola Bipolar Power Transistor Device Data
3–1
MJW16212
IC, COLLECTOR–EMITTER CURRENT (A)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
TJ = 25°C
1
2
3
MJH16212
DC
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN
5 ms
10
µs
100
ns
II
IC, COLLECTOR CURRENT (A)
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ELECTRICAL CHARACTERISTICS
(TC = 25
_
C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS (2)
Symbol
Min
Typ
Max
Unit
Collector Cutoff Current (VCE = 1500 V, VBE = 0 V)
Collector Cutoff Current
(VCE = 1200 V, VBE = 0 V)
Emitter–Base Leakage (VEB = 8.0 Vdc, IC = 0)
ICES
—
—
—
—
—
—
250
25
25
—
—
µAdc
µAdc
Vdc
Vdc
IEBO
Emitter–Base Breakdown Voltage (IE = 1.0 mA, IC = 0)
V(BR)EBO
8.0
11
—
Collector–Emitter Sustaining Voltage (Table 1) (IC = 10 mAdc, IB = 0)
VCEO(sus)
650
ON CHARACTERISTICS (2)
Collector–Emitter Saturation Voltage (IC = 5.5 Adc, IB = 2.2 Adc)
Collector–Emitter Saturation Voltage
(IC = 3.0 Adc, IB = 400 mAdc)
Base–Emitter Saturation Voltage (IC = 5.5 Adc, IB = 2.2 Adc)
DC Current Gain (IC = 1.0 A, VCE = 5.0 Vdc)
DC Current Gain
(IC = 10 A, VCE = 5.0 Vdc)
VCE(sat)
VBE(sat)
hFE
—
—
—
0.15
0.14
0.9
1.0
1.0
1.5
—
10
Vdc
Vdc
—
—
4.0
24
6.0
DYNAMIC CHARACTERISTICS
Dynamic Desaturation Interval (IC = 5.5 A, IB1 = 2.2 A, LB = 1.5
µH)
Output Capacitance
(VCE = 10 Vdc, IE = 0, ftest = 100 kHz)
tds
—
—
—
—
—
350
180
—
ns
Cob
fT
350
—
—
—
pF
Gain Bandwidth Product
(VCE = 10 Vdc, IC = 0.5 A, ftest = 1.0 MHz)
Emitter–Base Turn–Off Energy
(EB(avalanche) = 500 ns, RBE = 22
Ω)
2.75
35
MHz
µJ
EB(off)
Cc–hs
Collector–Heatsink Capacitance — MJF16212 Isolated Package
(Mounted on a 1″ x 2″ x 1/16″ Copper Heatsink, VCE = 0, ftest = 100 kHz)
5.0
pF
SWITCHING CHARACTERISTICS
Inductive Load (IC = 5.5 A, IB = 2.2 A), High Resolution Deflection
Simulator Circuit Table 2
Storage
Fall Time
ns
(2) Pulse Test: Pulse Width = 300
µs,
Duty Cycle
v
2.0%.
tsv
tfi
—
—
2000
200
4000
350
SAFE OPERATING AREA
100
50
20
18
IC/IB = 5
TJ
≤
100°C
14
10
6
2
0
300
600
900
1200
1500
5 7 10
20 30 50 70 100 200 300 500 700 1K
VCE, COLLECTOR–EMITTER VOLTAGE (V)
VCE, COLLECTOR–EMITTER VOLTAGE (V)
Figure 1. Maximum Forward Bias
Safe Operating Area
Figure 2. Maximum Reverse Bias
Safe Operating Area
3–2
Motorola Bipolar Power Transistor Device Data
MJW16212
SAFE OPERATING AREA (continued)
FORWARD BIAS
There are two limitations on the power handling ability of a
transistor: average junction temperature and second break-
down. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipa-
tion than the curves indicate.
The data of Figure 1 is based on TC = 25
_
C; T J(pk) is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC
≥
25
_
C. Second breakdown limitations do not der-
ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 1 may be found at any case tem-
perature by using the appropriate curve on Figure 3.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the limita-
tions imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases, with
the base–to–emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc.
The safe level for these devices is specified as Reverse
Biased Safe Operating Area and represents the voltage–
current condition allowable during reverse biased turnoff.
This rating is verified under clamped conditions so that the
device is never subjected to an avalanche mode. Figure 2
gives the RBSOA characteristics.
1
0.8
SECOND BREAKDOWN
DERATING
POWER DERATING FACTOR
0.6
THERMAL
DERATING
0.4
0.2
0
25
45
65
85
105
125
TC, CASE TEMPERATURE (°C)
Figure 3. Power Derating
Table 1. RBSOA/V(BR)CEO(SUS) Test Circuit
0.02
µF
H.P. 214
OR EQUIV.
P.G.
+
0
≈
– 35 V
0.02
µF
50
500
100
T1
0V
–V
(ICpk
[
LcoilCC )
V
A
50
*IB
Vclamp
VCC
IB
V(BR)CEO
L = 10 mH
RB2 =
∞
VCC = 20 Volts
*Tektronix
*P–6042
or
*Equivalent
RBSOA
L = 200
µH
RB2 = 0
VCC = 20 Volts
RB1 selected for desired IB1
IB2
IB1
T.U.T.
MR856
+V
IC
*IC
L
T1
VCE
VCE(pk)
–V
IC(pk)
+ –
1
µF
RB2
2N5337
–
100
+ V
≈
11 V
2N6191
20
10
µF
RB1
A
T1 adjusted to obtain IC(pk)
Note: Adjust – V to obtain desired VBE(off) at Point A.
Motorola Bipolar Power Transistor Device Data
3–3
MJW16212
VCE , COLLECTOR–EMITTER VOLTAGE (V)
VBE, BASE–EMITTER VOLTAGE (V)
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.01
.01 .02 .03 .05 0.1 0.2 0.3 0.5 1
2 3 5 7 10
IC = 2
4 5.5
8
10 A
10
7
5
3
2
= 25°C
1
0.7
0.5
0.3
0.2
0.1
0.1
IC/IB = 5
TJ = 100°C
TJ = 25°C
IC/IB = 10
TJ = 100°C
= 25°C
0.2
0.3
0.5 0.7
1
2
3
5
7
10
IB, BASE CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 4. Typical Collector–Emitter
Saturation Region
Figure 5. Typical Emitter–Base
Saturation Voltage
VCE , COLLECTOR–EMITTER VOLTAGE (V)
f
τ
, TRANSITION FREQUENCY
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
0.1
0.2
0.3
= 25°C
5
IC/IB = 10
TJ = 100°C
= 25°C
4
3
VCE = 10 V
f(test) = 1 MHz
TC = 25°C
IC/IB = 5
TJ = 100°C
2
1
0
0.5 0.7
1
2
3
5
7
10
0
1
2
3
4
5
6
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 6. Typical Collector–Emitter
Saturation Voltage
Figure 7. Typical Transition Frequency
10000
5000
2000
1000
500
200
100
50
20
10
5
2
1
1
2
3
5 7 10
20 30 50 70 100 200 300 500 1000
VR, REVERSE VOLTAGE (V)
ftest = 1 MHz
Cob
Cib
C, CAPACITANCE (pF)
Figure 8. Typical Capacitance
3–4
Motorola Bipolar Power Transistor Device Data
MJW16212
DYNAMIC DESATURATIION
The SCANSWITCH series of bipolar power transistors are
specifically designed to meet the unique requirements of hor-
izontal deflection circuits in computer monitor applications.
Historically, deflection transistor design was focused on mini-
mizing collector current fall time. While fall time is a valid
figure of merit, a more important indicator of circuit perfor-
mance as scan rates are increased is a new characteristic,
“dynamic desaturation.” In order to assure a linear collector
current ramp, the output transistor must remain in hard satu-
ration during storage time and exhibit a rapid turn–off transi-
tion. A sluggish transition results in serious consequences.
As the saturation voltage of the output transistor increases,
+ 24 V
the voltage across the yoke drops. Roll off in the collector
current ramp results in improper beam deflection and distor-
tion of the image at the right edge of the screen. Design
changes have been made in the structure of the SCANS-
WITCH series of devices which minimize the dynamic desa-
turation interval. Dynamic desaturation has been defined in
terms of the time required for the VCE to rise from 1.0 to
5.0 volts (Figures 9 and 10) and typical performance at opti-
mized drive conditions has been specified. Optimization of
device structure results in a linear collector current ramp, ex-
cellent turn–off switching performance, and significantly low-
er overall power dissipation.
Table 2. High Resolution Deflection Application Simulator
U2
MC7812
VI G VO
N
D
C2
10
µF
C1
100
µF
+
+
Q2
MJ11016
(IB)
R1
1k
6.2 V
R5
1k
(IC)
Q5
MJ11016
R7
2.7 k
R8
9.1 k
R9
470
+
R10
47
C3
10
µF
C6
100
µF
+
LY
C4
0.005
R2
R510
SYNC
Q1
R3
250
(DC)
8
C5
0.1
6
VCC
OUT
GND
2
1
100 V
R11
470
1W
Q3
MJE
15031
T1
R12
470
1W
LB
D2
MUR460
CY
7
OSC
%
R6
1k
U1
MC1391P
D1
MUR110
VCE
Q4
DUT
R4
22
BS170
T1: Ferroxcube Pot Core #1811 P3C8
Primary/Sec. Turns Ratio = 18:6
Gapped for LP = 30
µH
LB = 1.5
µH
CY = 0.01
µF
LY = 13
µH
5
DYNAMIC DESATURATION TIME
IS MEASURED FROM VCE = 1 V
TO VCE = 5 V
IB1 = 1.3 A
IB, BASE CURRENT (A)
VCE , COLLECTOR–EMITTER VOLTAGE (V)
4
3
2
IB2 = 4.9 A
1
0
0
2
4
TIME (ns)
6
8
tds
10
TIME (2
µs/DIV)
Figure 9. Deflection Simulator Circuit Base
Drive Waveform
Figure 10. Definition of Dynamic
Desaturation Measurement
Motorola Bipolar Power Transistor Device Data
3–5
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