4M x 8 SRAM MODULE
SYS84000RKX - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.6 : January 1999
Features
•
Access Times of 70/85/100/120 ns.
•
Low Power Disipation:
Operating
665 mW (Max.)
Standby-L Version (CMOS) 4.84mW (Max.)
•
5 Volt Supply ± 10%.
•
Completely Static Operation.
•
Equal Access and Cycle Times.
•
Low Voltage V
CC
Data Retention.
•
On-board Decoding & Capacitors.
•
38 Pin Single-In-Line package (SIP).
•
Upgrade path to SYS88000RKX (64Mbits).
Description
The SYS84000RKX is a plastic 32Mbit Static RAM
Module housed in a standard 38 pin Single In-Line
package organised as 4M x 8 with access times of 70,
85,100, or 120 ns.
The module is constructed using eight 512Kx8 SRAMs
in TSOPII packages mounted onto both sides of an FR4
epoxy substrate. This offers an extremely high PCB
packing density.
The device is offered in standard and low power versions,
with the -L module having a low voltage data retention
mode for battery backed applications. Buffering is
provided on the module to reduce the output capacitance
to 8pF(Typ).
Note: CS and OE on the module, should be used
with care to avoid on and off board bus contention.
Block Diagram
Pin Definition
NC
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
A21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
OE
WE
A0 - A18
512K x 8
SRAM
CS
CS
CS
CS
T/R
A19
A20
A21
Q0~3
DECODER
Q4~7
D0 - D7
D0 - D7
/8
CS
CS
512K x 8
SRAM
OE
CS
CS
CS
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A21
D0 - D7
CS
WE
OE
NC
V
CC
GND
Package Details
Plastic 38 pin Single-In-Line (SIP)
ISSUE 1.6 January 1999
SYS84000RKX - 70/85/10/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-55
Typ
-
-
-
Max
7.0
2.0
125
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
(Commercial)
(Industrial)
DC Electrical Characteristics
(V
CC
=5V±10%)
T
A
0 to 70
o
C
Parameter
I/P Leakage Current
Symbol Test Condition
Address,OE,WE
Min Typ
-8
-8
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
max
8
8
140
24
16
880
0.4
-
Unit
µA
µA
mA
mA
mA
mA
V
V
I
LI
I
LO
I
CC1
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min. Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 64.0mA
I
OH
= -15.0mA
Output Leakage Current
Operating Supply Current
Standby Supply Current
TTL levels
CMOS levels
-L Version (CMOS)
I
SB1
I
SB2
I
SB3
V
OL
V
OH
Output Voltage
Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
Add 420mA to -L & -P CMOS standby currents to obtain industrial temp range parameters.
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance
(Address,OE,WE)
I/P Capacitance
(other)
I/O Capacitance
Symbol Test Condition
C
IN1
C
IN2
C
I/O
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
64
12
12
Unit
pF
pF
pF
2
SYS84000RKX - 70/85/10/12
ISSUE 1.6 January 1999
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
L
H
H
WE
X
L
H
L
H
DATA PINS
High Impedance
Invalid State
Data Out
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
, I
SB4
~
I
CC1
I
CC1
I
CC1
MODE
Standby
Invalid
Read
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
OE must not be tied low permanently.
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
V
CC
for Data Retention
Data Retention Current
Symbol
V
DR
I
CCDR1 (2)
I
CCDR3
t
CDR
t
R
Test Condition
CS > V
CC
-0.2V
V
CC
= 3.0V, CS > V
CC
-0.2V
T
OP
= 0°C to 70°C
T
OP
= T
AI
See Retention Waveform
See Retention Waveform
min
2.0
-
-
0
5
typ
(1)
-
max
-
400
TBA
-
-
Unit
V
mA
mA
ns
ms
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes
-
-
-
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
ISSUE 1.6 January 1999
SYS84000RKX - 70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-70
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
-85
max
-
70
70
40
-
-
-
5
5
-10
max
-
85
85
50
-
-
-
5
5
-12
max
-
100
100
55
-
-
-
5
5
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
70
-
-
-
11.5
1.5
1.5
0
0
min
85
-
-
-
11.5
1.5
1.5
0
0
min
100
-
-
-
11.5
1.5
1.5
0
0
min
120
-
-
-
11.5
1.5
1.5
0
0
max
-
120
120
60
-
-
-
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-70
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
***
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write ***
-85
max
-
-
-
-
-
-
30
-
-
-
-10
min
100
80
80
0
70
5
0
45
0
5
-12
min
120
100
100
0
70
5
0
45
0
5
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
70
60
60
0
50
5
0
35
0
5
min
85
75
75
0
60
5
0
40
0
5
max
-
-
-
-
-
-
35
-
-
-
max
-
-
-
-
-
-
40
-
-
-
max
-
-
-
-
-
-
40
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*** Theses signals are the internal Ram signals on the module and are included to assist control signal
timing.
4
SYS84000RKX - 70/85/10/12
ISSUE 1.6 January 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
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