FAN7191-F085, FAD7191
600 V / 4.5 A, High and Low
Side Automotive Gate
Driver IC
Description
The FAN7191 / FAD7191 is a monolithic high− and low−side
gate−driver IC, which can drive high speed MOSFETs and IGBTs that
operate up to +600 V. It has a buffered output stage with all NMOS
transistors designed for high pulse driving capability and minimum
cross−conduction.
ON Semiconductor’s high−voltage process and common−mode
noise canceling technique provide stable operation of high−drivers
under high dV/dt noise circumstances. An advanced level−shift circuit
allows high−side gate driver operation up to V
S
= −9.8 V (typical) for
V
BS
= 15 V.
The UVLO circuit prevents malfunction when V
DD
and V
BS
are
lower than the specified threshold voltage.
The high current and low output voltage drop features make this
device suitable for controlling direct injection actuators and for use in
many automotive DC−DC converter and motor control applications.
Features
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SOIC8
CASE 751EB
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Floating Channel for Bootstrap Operation to +600 V
4.5 A Sourcing and 4.5 A Sinking Current Driving Capability
Common−Mode dV/dt Noise Cancelling Circuit
Built−in Under−Voltage Lockout for Both Channels
Matched Propagation Delay for Both Channels
3.3 V and 5 V Input Logic Compatible
Output In−phase with Input
Enable Pin (For 14−SOP Package Only)
14−SOP with Separate Signal and Power Ground for Enhanced Noise
Immunity
•
14−SOP with Increased Clearance for High Voltage Applications
•
Automotive Applications, AEC Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
Applications
SOIC14
CASE 751EF
ORDERING INFORMATION
Part Number
Package
Shipping
2500 / Tape & Reel
FAN7191MX−F085 8−SOP (751EB)
FAD7191M1X
14−SOP (751EF) 2500 / Tape & Reel
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Electric and Hybrid Electric Vehicles
48 V Mild Hybrid Vehicles
Automotive High Voltage DC−DC converters
Motor Control (Fans, Pumps, Compressors)
Advanced Fuel Injection Systems
Starter/Alternator
Electric Power Steering
MOSFET and IGBT Driver Applications
©
Semiconductor Components Industries, LLC, 2016
1
September, 2018 − Rev. 5
Publication Order Number:
FAN7191−F085/D
FAN7191−F085, FAD7191
Typical Application Circuit
Figure 1. Half−Bridge Application Circuit (8−SOP)
15 V
1
HIN
2
LIN
3
NC
14
V
B
13
HO
12
Controller
V
SS
4
EN
FAD7191* V
S
11
5
COM
6
LO
7
VDD
NC
10
NC
NC
C
BOOT
9
8
C
1
Figure 2. Half−Bridge Application Circuit (14−SOP)
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FAN7191−F085, FAD7191
INTERNAL BLOCK DIAGRAM
Figure 3. Functional Block Diagram (8−SOP)
Figure 4. Functional Block Diagram (14−SOP)
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FAN7191−F085, FAD7191
Pin Assignment
FAN7191*
FAD7191*
Figure 5.
Pin Assignments (Top View)
Table 1. PIN DEFINITIONS
8−Pin
1
2
3
14−Pin
1
2
3
4
5
4
5
6
7
8
6
7
11
12
13
8, 9, 10, 14
Name
HIN
LIN
V
SS
EN
COM
LO
V
DD
V
S
HO
V
B
NC
Description
Logic Input for High−Side Gate Driver Output
Logic Input for Low−Side Gate Driver Output
Logic Ground, Power ground for 8−SOP
Enable Input (Internal Pull Up)
Power Ground for 14−SOP, Low−side Driver Return
Low−Side Driver Output
Low−Side and Logic Power Supply Voltage
High−Side Floating Supply Return
High−Side Driver Output
High−Side Floating Supply
No Connect
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FAN7191−F085, FAD7191
Table 2. ABSOLUTE MAXIMUM RATINGS
(T
A
= −40°C to 125°C, unless otherwise specified. V
B
, V
DD
and V
IN
are referenced to V
SS
)
Symbol
V
S
V
B
V
HO
V
DD
COM
V
IN
V
LO
Parameter
High−side offset voltage VS
High−side floating supply voltage VB
High−side floating output voltage
Low−side and logic−fixed supply voltage
Power Ground (14−SOP)
Logic Input voltage (HIN, LIN, EN)
Low−Side Output Voltage LO (8−SOP)
Low−Side Output Voltage LO (14−SOP)
T
pulse
(Note 4)
d
VS/dt
P
D
(Note 1, 2, 3)
θ
JA
(Note 1, 2)
T
J
T
S
ESD
Minimum Pulse Width
Allowable offset voltage slew rate
Power Dissipation, T
A
= 25°C
8−SOP
14−SOP
Thermal Resistance, junction−to−ambient
8−SOP
14−SOP
Junction temperature
Storage temperature
Electrostatic
Discharge Capability
Human Body Model,
JESD22−A114
8−SOP
14−SOP
−55
Min.
V
B
− 25
−0.3
V
S
− 0.3
−0.3
V
DD
− 25
−0.3
V
SS
− 0.3
COM − 0.3
80
50
0.625
0.80
200
156
+150
+150
3000
2000
2000
Max.
V
B
+ 0.3
625
V
B
+ 0.3
25
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
V
V
V
V
V
V
V
ns
V/ns
W
W
°C/W
°C/W
°C
°C
V
Charged Device Model, JESD22−C101
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 76.2
×
114.3
×
1.6 mm PCB (FR−4 glass epoxy material).
2. Refer to the following standards: JESD51−2: Integral circuits thermal test method environmental conditions – natural convection.
JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages.
3. P
D
is the power that raises T
J
to 150°C for T
A
= 25°C. P
D
to be derated at higher ambient temperature.
4. Minimum input pulse width that guarantee to produce an output pulse. Valid for turn on and turn off pulse width.
Table 3. RECOMMENDED OPERATING CONDITIONS
(V
S
, V
DD
and V
IN
are referenced to V
SS
)
Symbol
V
B
V
S
V
HO
V
DD
V
LO
V
IN
COM
T
A
Parameter
High−side floating supply voltage
High−side Floating Supply Offset Voltage
High−side Output Voltage
Low−side and Logic Supply voltage
Low−side output voltage (8−SOP)
Low−side output voltage (14−SOP)
Logic input voltage (HIN, LIN, EN)
Power Ground (14−SOP)
Ambient Temperature
Min.
V
S
+ 10
6 − V
BS
V
S
10
0
COM
0
V
DD
− 22
−40
Max.
V
S
+ 22
600
V
B
22
V
DD
V
DD
V
DD
V
DD
+125
Unit
V
V
V
V
V
V
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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