Advance Information
W130
Spread Spectrum Desktop / Notebook System Clock
Features
• Maximized EMI suppression using IC WORKS’ Spread
Spectrum Technology
• Six copies of CPU Clock
• Eight copies of PCI Clock (Synchronous w/CPU clock)
• Two copies of 14.318MHz IOAPIC Clock
• Two copies of 48MHz USB Clock
• Three buffered copies of 14.318MHz reference input
• Input is a 14.318MHz XTAL or reference signal
• Selectable 100MHz or 66MHz CPU Clocks
• Power management control input pins
Key Specifications
Supply Voltages:
VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Clock Jitter:
200ps
CPU0:5 Clock Skew:
175ps
PCI_F, PCI1:7 Clock Skew:
500ps
CPU to PCI Clock Skew:1.5 - 4.0 ns (CPU Leads)
Test mode and output tristate
Logic inputs have 250K ohm pull-up resistor except SEL100/66#
Figure 1 Block Diagram
VDDQ3
REF0
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
APIC0
APIC1
VDDQ2
CPU_STOP#
Stop
Clock
Control
100/66#_SEL
SEL0
SEL1
SPREAD#
PLL 1
÷2/÷3
CPU0
CPU1
CPU2
CPU3
CPU4
CPU5
VDDQ3
PCI_F
Stop
Clock
Control
PCI_STOP#
VDDQ3
PCI4
PCI5
PCI6
PCI7
PWR_DWN#
Power
Power
Down
Down
Control
Control
VDDQ3
PLL2
48MHz
48MHz
PCI1
PCI2
PCI3
REF1
REF2
Table 1
SEL
100/66#
0
0
0
0
1
1
1
1
Pin Selectable Frequency (Note)
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
66.6
66.6
66.6
X1/2
100
100
100
PCI
HI-Z
33.3
33.3
33.3
X1/6
33.3
33.3
33.3
SPREAD#=0
Don’ Care
t
±
0.9% Center
-
1% Down
-
0.5% Down
Don’ Care
t
±
0.9% Center
-
1% Down
-
0.5% Down
Figure 2 Pin Diagram
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
GND
VDDQ2
CPU4
CPU5
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL0
SEL1
SEL100/66#
Table 2
W130
Order Information
Package
H = SSOP (300 mils)
Part Number
May 1998
Revision 0.1
IC WORKS · 3725 North First Street · San Jose, CA 95134-1700 · (408) 922-0202
Advance Information
W130
Pin Definitions
Pin Name
CPU0:5
Pin
No.
42,41,40,
39, 36, 35
8, 10, 11,
13, 14, 16,
17
7
Pin
Type
O
Pin Description
CPU Clock Outputs 0 through 5:
These six CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ2.
PCI Bus Clock Outputs 1 through 7:
These seven PCI clock outputs are con-
trolled by the PCI_STOP# control pin. Output voltage swing is controlled by volt-
age applied to VDDQ3.
Fixed PCI Clock Output:
Unlike PCI1:7 outputs, this output is not controlled by
the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
CPU_STOP# input:
When brought low, clock outputs CPU0:5 are stopped low
after completing a full clock cycle (2-3 CPU clock latency). When brought high,
clock outputs CPU0:5 start beginning with a full clock cycle (2-3 CPU clock
latency).
PCI_STOP# Input:
The PCI_STOP# input enables the PCI 1:7 outputs when high
and causes them to remain at logic 0 when low. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle.
SPREAD# Input:
When brought low this pin activates Spread Spectrum clocking.
I/O APIC Clock Outputs:
Provides 14.318MHz fixed frequency. The output volt-
age swing is controlled by VDDQ2.
48MHz Outputs:
Fixed clock outputs at 48MHz. Output voltage swing is con-
trolled by voltage applied to VDDQ3.
Fixed 14.318MHz Outputs 0 through 2:
Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
Frequency Selection Input:
Selects power-up default CPU clock frequency as
shown in Table 1 on page 1.
Crystal Connection or External Reference Frequency Input:
Connect to either
a 14.318MHz crystal or reference signal.
Crystal Connection:
An input connection for an external 14.318MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control:
When this input is low, device goes into a low power con-
dition. All outputs are held low while in power down. CPU and PCI clock outputs
are stopped low after completing a full clock cycle (2-3 CPU clock cycle latency).
When brought high, CPU, SDRAM and PCI outputs start with a full clock cycle at
full operating frequency (3ms maximum latency).
Power Connection:
Power supply for core logic, PLL circuitry, PCI output buff-
ers, reference output buffers, and 48 MHz output buffers. Connected to 3.3V sup-
ply.
Power Connection:
Power supply for APIC0:1and CPU0:5 output buffers. Con-
nected to 2.5V supply.
Ground Connection:
Connect all ground pins to the common system ground
plane.
PCI1:7
O
PCI_F
O
CPU_STOP#
30
I
PCI_STOP#
31
I
SPREAD#
APIC0:1
48MHz
REF0:2
SEL100/66#
SEL1, SEL0
X1
X2
PWR_DWN#
28
45, 44
22, 23
1, 2, 47
25, 26, 27
4
5
29
I
O
O
O
I
I
I
I
VDDQ3
9,15,19, 21,
33, 48
37,43,46
3, 6, 12, 18,
20, 24, 32,
34, 38
P
VDDQ2
GND
P
G
Page 2
Spread Spectrum Desktop / Notebook System Clock
Revision 0.1
Advance Information
W130
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increas-
ing the bandwidth of the fundamental and its harmonics, the
amplitudes of the radiated electromagnetic emissions are
reduced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal.
The reduction in amplitude is dependent on the harmonic
number and the frequency deviation or spread. The equation
for the reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where
P
is the percentage of deviation and
F
is the fre-
quency in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions"
by Bush, Fessler, and Hardin, produces the maximum reduc-
tion in the amplitude of radiated electromagnetic emissions.
The deviation selected for this chip is - 0.5%, ±0.9%, or -1.0%
of the selected frequency. Figure 6 details the IC WORKS
spreading pattern. IC WORKS does offer options with more
spread and greater EMI reduction. Contact your local Sales
representative for details on these devices.
Figure 3 Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Spread Spectrum clocking is activated or deactivated by SPREAD# input (pin 28).
Figure 4 Typical Modulation Profile
MAX (+.0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN. (- 0.5%)
Spread Spectrum Desktop / Notebook System Clock
Revision 0.1
100%
Page 3
Advance Information
W130
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other con-
Symbol
V
DD
, V
IN
T
STG
T
B
T
A
ESD
PROT
Parameter
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature under Bias
Operating Temperature
Input ESD Protection
ditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
2 (min)
Unit
V
°C
°C
°C
kV
DC Electrical Characteristics:
T
A
= 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
Supply Current
I
DDQ3
I
DDQ2
Logic Inputs
V
IL
V
IH
I
IL
I
IH
I
IL
I
IH
Input Low Voltage
Input High Voltage
Input Low Current (Note 2)
Input High Current (Note 2)
Input Low Current (SEL100/66#)
Input High Current (SEL100/66#)
GND -.3
2.0
0.8
VDD +.3
-25
10
-5
+5
V
V
µA
µA
µA
µA
3.3V Supply Current
3.3V Supply Current
95
75
mA
CPU0:5 = 100MHz
Outputs Loaded (Note 1)
CPU0:5 = 100MHz
Outputs Loaded (Note 1)
Clock Outputs
V
OL
V
OH
V
OH
I
OL
Output Low Voltage
Output High Voltage
Output High Voltage
Output Low Current:
CPU0:5,
APIC0:1
CPU0:5
PCI_F, PCI1:7
APIC0:1
REF0:2
48MHz
3.1
2.2
27
20.5
40
25
25
57
53
85
37
37
97
139
140
76
76
50
mV
V
V
mA
mA
mA
mA
mA
I
OL
= 1mA
I
OH
= –1mA
I
OL
= –1mA
V
OL
= 1.25V
V
OL
= 1.5V
V
OL
= 1.25V
V
OL
= 1.5V
V
OL
= 1.5V
Page 4
Spread Spectrum Desktop / Notebook System Clock
Revision 0.1
Advance Information
W130
DC Electrical Characteristics:
Symbol
I
OH
Parameter
Output High Current
CPU0:5
PCI_F, PCI1:7
IOAPIC
REF0:2
48MHz
Crystal Oscillator
V
TH
C
LOAD
C
IN,X1
X1 Input threshold Voltage (Note 3)
Load Capacitance, As seen by
External Crystal (Note 4)
X1 Input Capacitance (Note 5)
1.65
14
28
V
pF
pF
Pin X2 unconnected
VDDQ3 = 3.3V
(cont.)
T
A
= 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%
Min
25
31
40
27
27
Typ
55
55
87
44
44
Max
97
189
155
94
94
Unit
mA
mA
mA
mA
mA
Test Condition
V
OH
= 1.25V
V
OH
= 1.5V
V
OH
= 1.25V
V
OH
= 1.5V
V
OH
= 1.5V
Pin Capacitance/Inductance
C
IN
C
OUT
L
IN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
Except X1 and X2
Notes:
1. All clock outputs loaded with 6" 60ohm traces with 22pF capacitors.
2. W130 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level).
3. X1 input threshold voltage (typical) is VDD/2.
4. The W130 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total
load placed on crystal is 14pF; this includes typical stray capacitance of short PCB traces to crystal.
5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Spread Spectrum Desktop / Notebook System Clock
Revision 0.1
Page 5
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