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CAT22C10LA-30

产品描述IC 64 X 4 NON-VOLATILE SRAM, 300 ns, PDIP18, LEAD AND HALOGEN FREE, PLASTIC, DIP-18, Static RAM
产品类别存储    存储   
文件大小57KB,共10页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
标准  
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CAT22C10LA-30概述

IC 64 X 4 NON-VOLATILE SRAM, 300 ns, PDIP18, LEAD AND HALOGEN FREE, PLASTIC, DIP-18, Static RAM

CAT22C10LA-30规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称ON Semiconductor(安森美)
零件包装代码DIP
包装说明DIP,
针数18
Reach Compliance Codecompliant
ECCN代码EAR99
最长访问时间300 ns
JESD-30 代码R-PDIP-T18
JESD-609代码e3
长度21.97 mm
内存密度256 bit
内存集成电路类型NON-VOLATILE SRAM
内存宽度4
功能数量1
端子数量18
字数64 words
字数代码64
工作模式ASYNCHRONOUS
最高工作温度105 °C
最低工作温度-40 °C
组织64X4
封装主体材料PLASTIC/EPOXY
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)260
认证状态Not Qualified
座面最大高度4.57 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
宽度7.62 mm

文档预览

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CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
s
Single 5V Supply
s
Fast RAM Access Times:
s
Low CMOS Power Consumption:
–200ns
–300ns
s
Infinite EEPROM to RAM Recall
s
CMOS and TTL Compatible I/O
s
Power Up/Down Protection
s
100,000 Program/Erase Cycles (E
2
PROM)
–Active: 40mA Max.
–Standby: 30
µ
A Max.
s
JEDEC Standard Pinouts:
–18-lead DIP
–16-lead SOIC
s
10 Year Data Retention
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory
organized as 64 words x 4 bits. The high speed Static
RAM array is bit for bit backed up by a nonvolatile
EEPROM array which allows for easy transfer of data
from RAM array to EEPROM (STORE) and from
EEPROM to RAM (RECALL). STORE operations are
completed in 10ms max. and RECALL operations typi-
cally within 1.5µs. The CAT22C10 features unlimited
RAM write operations either through external RAM
writes or internal recalls from EEPROM. Internal false
store protection circuitry prohibits STORE operations
when V
CC
is less than 3.0V.
The CAT22C10 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles (EEPROM)
and has a data retention of 10 years. The device is
available in JEDEC approved 18-lead plastic DIP and
16-lead SOIC packages.
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
A4
A3
A2
A1
A0
CS
Vss
STORE
PIN FUNCTIONS
Pin Name
A
0
–A
5
Function
Address
Data In/Out
Write Enable
Chip Select
Recall
Store
+5V
Ground
No Connect
NC
A4
A3
A2
A1
A0
CS
Vss
STORE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
Vcc
NC
A5
I/O3
I/O2
I/O1
I/O0
WE
RECALL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vcc
A5
I/O4
I/O3
I/O2
I/O1
WE
RECALL
I/O
0
–I/O
3
WE
CS
RECALL
STORE
V
CC
V
SS
NC
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
1
Doc. No. MD-1082, Rev. R

 
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