REVISIONS
LTR
A
B
DESCRIPTION
Add case outline Y. Change memory skew timing , t9, in Table I. - PHN
Change the maximum values of Core supply voltage and I/O supply voltage in section
1.3. Change and add the tests for t
22
, t
23a
, t
23b
, t
24
in Table IA. Change Figure 13 and
add Figure 14 for timing waveforms and test circuits. Update boilerplate to current
MIL-PRF-38535 requirements. - PHN
DATE (
YR-MO-DA
)
10-01-06
13-02-19
APPROVED
Thomas M. Hess
Thomas M. Hess
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
B
35
B
15
B
36
B
16
B
37
B
17
B
38
B
18
REV
B
39
B
19
B
40
B
20
B
41
B
21
B
1
B
42
B
22
B
2
B
43
B
23
B
3
B
44
B
24
B
4
B
45
B
25
B
5
B
46
B
26
B
6
B
27
B
7
B
28
B
8
B
29
B
9
B
30
B
10
B
31
B
11
B
32
B
12
B
33
B
13
B
34
B
14
SHEET
PREPARED BY
PMIC N/A
Charles F. Saffle
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Charles F. Saffle
APPROVED BY
Thomas M. Hess
DRAWING APPROVAL DATE
09-05-28
REVISION LEVEL
SIZE
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
MICROCIRCUIT, DIGITAL, CMOS, RADIATION
HARDENED, 32-BIT FAULT-TOLERANT V8/LEON 3FT
PROCESSOR, MONOLITHIC SILICON
CAGE CODE
AMSC N/A
B
A
SHEET
1
67268
OF
46
5962-08228
DSCC FORM 2233
APR 97
5962-E271-13
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
F
08228
01
V
X
C
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
/
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
1/
1/
Generic number
UT699
UT699
Circuit function
32-bit fault-tolerant V8/LEON 3FT processor
32-bit fault-tolerant V8/LEON 3FT processor
With additional screening 2/
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Q or V
Device requirements documentation
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Descriptive designator
See figure 1
See figure 1
Terminals
352
484
Package style
Ceramic quad flat-pack
Ceramic land grid array
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
.
__________
1/
2/
This device has restricted temperature range of -40°C to +105°C.
Device type 02 provides a QML class Q product with the additional testing as specified in paragraph 4.4.2.d herein.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-08228
SHEET
2
B
1.3 Absolute maximum ratings.
1/ 2/
-0.3 V dc to 3.6 V dc
-0.3 V dc to 4.3 V dc
V
SS
- 0.3 V dc to V
DD
+ 0.3 V dc
9 W 3/
-65°C to 150°C
150°C 4/
5°C/W
-40°C to +105°C
2000 V
Core supply voltage range (V
DDC
) ..............................................................................
I/O supply voltage range (V
DD
)...................................................................................
Input voltage range on any pin (V
IN
) ..........................................................................
Power dissipation (P
D
) (T
C
= 105°C)..........................................................................
Storage temperature range (T
STG
) .............................................................................
Maximum junction temperature (T
J
) ...........................................................................
Thermal resistance, junction to case (θ
JC
) .................................................................
Case operating temperature range (T
C
) .....................................................................
Minimum ESD protection (human body model) (ESD
HBM
) ..........................................
1.4 Recommended operating conditions.
Core supply voltage range (V
DDC
) ..............................................................................
I/O supply voltage range (V
DD
)...................................................................................
Input voltage range on any pin (V
IN
) ..........................................................................
Case operating temperature range (T
C
) .....................................................................
Maximum rise time, all CMOS and PCI inputs (t
r
) ......................................................
Maximum fall time, all CMOS and PCI inputs (t
f
) .......................................................
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s) ..............................
Single event phenomenon (SEP):
Linear energy transfer (LET) with no latchup (SEL) ............................................
Linear energy transfer (LET) with no upset (SEU) ..............................................
Neutron fluence ........................................................................................................
2.3 V dc to 2.7 V dc
3.0 V dc to 3.6 V dc
0 V dc to V
DD
-40°C to +105°C
20 ns
20 ns
≥
300 krad (Si)
≥
108 MeV-cm /mg
2
≥
54 MeV-cm /mg
14
2
≥
1 x 10 neutrons/cm
2
5/ 6/
5/ 7/
5/
__________
1/
2/
3/
4/
5/
6/
7/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
All voltage values are with respect to V
SS
(Ground).
Per MIL-STD-883, method 1012, section 3.4.1, P
D
= (T
J
(max) – T
C
(max))/θ
JC
.
Maximum junction temperature may be increased to +175°C during burn-in and steady-state life testing.
Limits are guaranteed by design or process but not production tested unless specified by the customer through the
purchase order or contract.
Worst case temperature and voltage of T
A
= +125°C, V
DD
= 3.6 V, V
DDC
= 2.7 V.
Onset LET is for flip-flop memory. Single event upsets for embedded RAM memory are driven by charged particle flux,
rather than 'LET', due to the fault tolerant design architecture. Contact manufacturer for details.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-08228
SHEET
3
B
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535
-
Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
-
List of Standard Microcircuit Drawings
Standard Microcircuit Drawings.
(Copies of these documents are available online at
http://assist.daps.dla.mil/quicksearch/
or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by
Heavy Ion Irradiation of Semiconductor Devices
(Copies of this document are available online at
http://www.astm.org/
or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA 19428-2959).
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture.
(Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
Piscataway, NJ 08854-4150).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-08228
SHEET
4
B
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and on figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3.
3.2.4 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as specified on figures 4 through 17.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
3.8 IEEE 1149.1 compliance. These devices shall be compliant to IEEE 1149.1.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-08228
SHEET
5
B
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