MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTB2N60E/D
™
Data Sheet
TMOS E-FET.
™
High Energy Power FET
D2PAK for Surface Mount
Designer's
MTB2N60E
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp
≤
10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 2.0 Apk, L = 95 mH, RG = 25
Ω)
Thermal Resistance
— Junction to Case
— Junction to Ambient
— Junction to Ambient (1)
TMOS POWER FET
2.0 AMPERES
600 VOLTS
RDS(on) = 3.8 OHM
®
D
G
CASE 418B–02, Style 2
D2PAK
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
600
600
±
20
±
40
2.0
1.3
7.0
50
0.4
2.5
– 55 to 150
190
2.5
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
TJ, Tstg
EAS
R
θJC
R
θJA
R
θJA
TL
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MTB2N60E
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
(VDD = 300 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 18
Ω)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
LD
—
LS
—
7.5
—
3.5
—
nH
nH
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
VSD
trr
—
340
—
—
—
1.0
0.9
1.6
—
Vdc
ns
—
—
—
—
—
—
—
—
12
21
30
24
13
2.0
6.0
5.0
—
—
—
—
—
—
—
—
nC
ns
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
435
100
20
—
—
—
pF
VGS(th)
2.0
—
RDS(on)
VDS(on)
—
—
gFS
1.0
—
—
—
8.2
8.4
—
mhos
—
3.1
8.5
3.0
4.0
—
3.8
Vdc
mV/°C
Ohm
Vdc
V(BR)DSS
600
—
IDSS
—
—
IGSS
—
—
—
—
0.25
1.0
100
nAdc
—
480
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB2N60E
TYPICAL ELECTRICAL CHARACTERISTICS
4
ID , DRAIN CURRENT (AMPS)
TJ = 25°C
VGS = 10 V
8
7V
ID , DRAIN CURRENT (AMPS)
6
VDS
≥
10 V
3
6V
2
5.5 V
1
5V
0
0
4
8
12
16
20
4
TJ = 100°C
–55°C
25°C
0
0
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
2
10
2
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
12
VGS = 10 V
100°C
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
0
0.5
1
1.5
2
2.5
3
ID, DRAIN CURRENT (AMPS)
3.5
4
15 V
VGS = 10 V
TJ = 25°C
8
TJ = 25°C
4
–55°C
0
0
1.5
3
ID, DRAIN CURRENT (AMPS)
4.5
6
Figure 3. On–Resistance versus Drain Current
and Temperature
1000
VGS = 10 V
ID = 1 A
2
I DSS , LEAKAGE (nA)
100
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.5
VGS = 0 V
TJ = 125°C
100°C
1.5
1
10
0.5
0
– 50
– 25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
1
0
100
300
500
200
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
600
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB2N60E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
800
700
600
C, CAPACITANCE (pF)
500
400
300
200
100
0
10
VDS = 0 V
Ciss
VGS = 0 V
TJ = 25°C
1000
Ciss
C, CAPACITANCE (pF)
100
Coss
10
Crss
1
TJ = 25°C
VGS = 0
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
Ciss
Crss
Coss
Crss
5
0
5
10
15
20
25
0.1
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance
Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTB2N60E
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)
15
12
VDS
500
TJ = 25°C
ID = 2 A
400
QT
Q1
Q2
3
VGS
Q3
4
8
12
16
20
100
0
VDS = 100 V
VDS = 250 V
VDS = 400 V
1000
TJ = 25°C
ID = 2 A
VDS = 300 V
VGS = 10 V
td(off)
tf
tr
100
t, TIME (ns)
9
6
300
200
td(on)
10
00
1
1
10
100
RG, GATE RESISTANCE (OHMS)
1000
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
2.0
1.8
I S , SOURCE CURRENT (AMPS)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
VGS = 0 V
TJ = 25°C
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–Gener-
al Data and Its Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
µs.
In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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