MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
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by MTB15N06V/D
TMOS
Power Field Effect Transistor
D2PAK for Surface Mount
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
•
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
•
Faster Switching than E–FET Predecessors
™
Data Sheet
V
™
MTB15N06V
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
N–Channel Enhancement–Mode Silicon Gate
TM
D
G
S
CASE 418B–02, Style 2
D2PAK
Features Common to TMOS V and TMOS E–FETs
•
Avalanche Energy Specified
•
IDSS and VDS(on) Specified at Elevated Temperature
•
Static Parameters are the Same for both TMOS V and TMOS E–FET
•
Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Non–Repetitive (tp
≤
10 ms)
Drain Current — Continuous @ 25°C
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25
Ω)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
60
60
±
20
±
25
15
8.7
45
55
0.37
3.0
– 55 to 175
113
2.73
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
TJ, Tstg
EAS
R
θJC
R
θJA
R
θJA
TL
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
©
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MTB15N06V
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 7.5 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150°C)
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc)
(VDD = 30 Vdc, ID = 15 Adc,
VGS = 10 Vdc,
RG = 9.1
Ω)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
—
—
trr
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
LD
LS
—
—
4.5
7.5
—
—
nH
nH
ta
tb
QRR
—
—
—
—
1.05
0.9
59.3
46
13.3
0.165
1.6
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
7.6
51
18
33
14.4
2.8
6.4
6.1
20
100
40
70
20
—
—
—
nC
ns
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
469
148
35
660
200
60
pF
VGS(th)
2.0
—
RDS(on)
VDS(on)
—
—
gFS
4.0
2.0
—
6.2
2.2
1.9
—
mhos
—
2.7
5.0
0.08
4.0
—
0.12
Vdc
mV/°C
Ohm
Vdc
V(BR)DSS
60
—
IDSS
—
—
IGSS
—
—
—
—
10
100
100
nAdc
—
67
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(See Figure 14)
2
Motorola TMOS Power MOSFET Transistor Device Data
MTB15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
25
20
15
10
5
0
0
1
2
3
4
5
6
7
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
5V
VGS = 10 V
9V
30
8V
7V
I D , DRAIN CURRENT (AMPS)
25
100°C
20
15
10
5
0
2
4
6
8
10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
25°C
TJ = – 55°C
VDS
≥
10 V
6V
Figure 1. On–Region Characteristics
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.2
VGS = 10 V
0.13
TJ = 25°C
0.11
0.14
TJ = 100°C
0.09
VGS = 10 V
25°C
0.08
– 55°C
15 V
0.07
0.02
0
5
10
15
20
25
30
ID, DRAIN CURRENT (AMPS)
0.05
0
5
10
15
20
25
30
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2
VGS = 10 V
ID = 7.5 A
1.6
I DSS , LEAKAGE (nA)
100
VGS = 0 V
1.2
TJ = 125°C
0.8
0.4
– 50
– 25
0
25
50
75
100
125
150
175
10
0
10
20
30
40
50
60
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB15N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500
1200
C, CAPACITANCE (pF)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.
VDS = 0 V
Ciss
VGS = 0 V
TJ = 25°C
900
Crss
600
Ciss
Coss
Crss
0
10
5
VGS
0
VDS
5
10
15
20
25
300
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTB15N06V
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
12
10
8
Q1
6
4
2
0
0
Q3
3
6
9
QT, TOTAL CHARGE (nC)
VDS
12
ID = 15 A
TJ = 25°C
Q2
30
20
10
0
15
QT
VGS
40
60
50
1000
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25°C
tr
tf
td(off)
10
td(on)
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
100
1
1
10
RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
15
12
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
9
6
3
0
0.5
0.7
0.9
1.1
1.3
1.5
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10
µs.
In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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