SYS82000FK - 20/25/35
ISSUE 1.1 February 1999
2M x 8 SRAM MODULE
SYS82000FK - 020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.1 : February 1999
Features
•
•
•
•
Access Times of 20/25/35 ns.
36 Pin JEDEC standard Dual-In-Line package.
5 Volt Supply ± 10%.
Low Power Dissipation:
Average (min cycle)
2.15W (max).
Standby (
-L Version CMOS
) 220mW (max).
Completely Static Operation.
Low Voltage V
CC
Data Retention.
Equal Access and Cycle Times.
On-board Supply Decoupling Capacitors.
Description
The SYS82000FK is a plastic 16Mbit Static RAM
Module housed in a JEDEC standard 36 pin Dual
In-Line package organised as 2Mx8.
The module utilises 512Kx8 SRAM's housed in
SOJ packages, and uses double sided surface
mount techniques, buried decoder and dual board
construction to achieve a very high density module,
emulating the 16Mbit monolithic pinout.
Access times of 20 to 35 ns are available. The OE
pin allows faster access times than address access
during a read cycle.
•
•
•
•
Block Diagram
A0 - A18
D0 - D7
WE
OE
Pin Definition
512K X 8
SRAM
CS
512K X 8
SRAM
CS
512K X 8
SRAM
CS
512K X 8
SRAM
CS
CS
A19
A20
DECODER
Pin Functions
A0
A1
A2
A3
A4
CS
D0
D1
Vcc
GND
D2
D3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
TOP VIEW
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A20
A19
A18
A17
A16
OE
D7
D6
GND
Vcc
D5
D4
A15
A14
A13
A12
A11
A10
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
Ground
A0 ~ A20
D0 ~ D7
CS
WE
OE
V
CC
GND
Package Details
Plastic 36 Pin 0.6" Dual-In-Line
Package.(DIP)
1
ISSUE 1.1 February 1999
SYS82000FK - 20/25/35
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-55
Typ
-
1.0
-
Max
7.0
-
125
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -3.0V pulse of less than 30ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
Vcc+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
(Commercial)
(Industrial)
DC Electrical Characteristics
(V
CC
=5V±10%)
T
A
0 to 70
o
C
Parameter
I/P Leakage Current
Symbol Test Condition
Address,OE,WE
Min Typ
-20
-20
-
-
-
-
2.4
-
-
-
-
-
-
-
max
20
20
390
240
60
0.4
-
Unit
µA
µA
mA
mA
mA
V
V
I
LI
I
LO
I
CC1
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
, OE=V
IH
Min. Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Output Leakage Current
Operating Supply Current
Standby Supply Current
Output Voltage
TTL levels
CMOS levels
I
SB1
I
SB2
V
OL
V
OH
Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance
(Address,OE,WE)
Input Capacitance
(other)
I/O Capacitance
Symbol Test Condition
C
IN1
C
IN2
C
I/O
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
35
10
47
Unit
pF
pF
pF
2
SYS82000FK - 20/25/35
ISSUE 1.1 February 1999
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
Output Load
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
DATA PINS
High Impedance
Data Out
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
I
CC1
I
CC1
I
SB1
, I
SB2
, I
SB3
MODE
Standby
Read
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Symbol
V
DR
I
CCDR1
t
CDR
t
R
Test Condition
min
typ
-
-
-
-
max
-
2.4
-
-
Unit
V
mA
ns
ms
Operation Recovery Time
Notes
CS > V
CC
-0.2V
2.0
2.0 < Vcc < 5.5V,CS>Vcc-0.2 -
See Retention Waveform
0
See Retention Waveform
t
RC
(1) Figures are measured over the comercial Temp range.
3
ISSUE 1.1 February 1999
SYS82000FK - 20/25/35
AC OPERATING CONDITIONS
Read Cycle
-020
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
20
-
-
-
3
0
0
0
0
max
-
20
20
10
-
-
-
9
9
-025
min
25
-
-
-
3
0
0
0
0
max
-
25
25
12
-
-
-
10
10
-035
min
35
-
-
-
5
0
0
0
0
max Unit
-
35
35
14
-
-
-
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-20
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
15
15
0
15
0
0
10
0
3
max
-
-
-
-
-
-
9
-
-
-
-25
min
25
17
17
0
17
0
0
12
0
5
max
-
-
-
-
-
-
10
-
-
-
-35
min
35
20
20
0
20
3
0
20
0
5
max Unit
-
-
-
-
-
-
15
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS82000FK - 20/25/35
ISSUE 1.1 February 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
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