MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMFT1N10E/D
Medium Power Field Effect Transistor
N–Channel Enhancement Mode
Silicon Gate TMOS E–FET
t
SOT–223 for Surface Mount
This advanced E–FET is a TMOS Medium Power MOSFET
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient device also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
dc–dc converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients. The device is
housed in the SOT–223 package which is designed for medium
power surface mount applications.
•
Silicon Gate for Fast Switching Speeds
•
Low RDS(on) — 0.25
Ω
max
•
The SOT–223 Package can be Soldered Using Wave or Re-
flow. The Formed Leads Absorb Thermal Stress During Sol-
dering, Eliminating the Possibility of Damage to the Die
•
Available in 12 mm Tape and Reel
Use MMFT1N10ET1 to order the 7 inch/1000 unit reel.
Use MMFT1N10ET3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Drain Current
— Pulsed
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 60 V, VGS = 10 V, Peak IL= 1 A, L = 0.2 mH, RG = 25
Ω)
Symbol
VDS
VGS
ID
IDM
PD(1)
TJ, Tstg
EAS
1
G
S
3
MMFT1N10E
Motorola Preferred Device
®
MEDIUM POWER
TMOS FET
1 AMP
100 VOLTS
RDS(on) = 0.25 OHM
2,4
D
1
4
2
3
CASE 318E–04, STYLE 3
TO–261AA
Value
100
±
20
1
4
0.8
6.4
– 65 to 150
168
Unit
Vdc
Adc
Watts
mW/°C
°C
mJ
DEVICE MARKING
1N10
THERMAL CHARACTERISTICS
Thermal Resistance — Junction–to–Ambient (surface mounted)
Maximum Temperature for Soldering Purposes,
Time in Solder Bath
R
θJA
TL
156
260
10
°C/W
°C
Sec
(1) Power rating when mounted on FR–4 glass epoxy printed circuit board using recommended footprint.
TMOS is a registered trademark of Motorola, Inc.
E–FET is a trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 3
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1995
1
MMFT1N10E
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250
µA)
Zero Gate Voltage Drain Current, (VDS = 100 V, VGS = 0)
Gate–Body Leakage Current, (VGS = 20 V, VDS = 0)
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA)
Static Drain–to–Source On–Resistance, (VGS = 10 V, ID = 0.5 A)
Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1 A)
Forward Transconductance, (VDS = 10 V, ID = 0.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
(VDS = 80 V, ID = 1 A,
VGS = 10 Vdc)
See Figures 15 and 16
(VDD = 25 V, ID = 0.5 A
VGS = 10 V, RG = 50 ohms,
RGS = 25 ohms)
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
—
—
—
—
—
—
—
15
15
30
32
7
1.3
3.2
—
—
ns
—
—
—
—
—
nC
(VDS = 20 V,
VGS = 0,
f = 1 MHz)
Ciss
Coss
Crss
—
—
—
410
145
55
—
—
—
pF
VGS(th)
RDS(on)
VDS(on)
gFS
2
—
—
—
—
—
—
2.2
4.5
0.25
0.33
—
Vdc
Ohms
Vdc
mhos
V(BR)DSS
IDSS
IGSS
100
—
—
—
—
—
—
10
100
Vdc
µAdc
nAdc
Symbol
Min
Typ
Max
Unit
SOURCE DRAIN DIODE CHARACTERISTICS(1)
Forward On–Voltage
Forward Turn–On Time
Reverse Recovery Time
IS = 1 A, VGS = 0
IS = 1 A, VGS = 0,
dlS/dt = 400 A/µs,
VR = 50 V
VSD
ton
trr
—
—
0.8
—
Vdc
Limited by stray inductance
90
—
ns
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%
2
Motorola TMOS Power MOSFET Transistor Device Data
MMFT1N10E
10
8
TJ = 25°C
6V
6
VGS(TH), GATE THRESHOLD VOLTAGE
(NORMALIZED)
10 V
9V
8V
7V
1.2
VDS = VGS
ID = 1.0 mA
1.1
I D, DRAIN CURRENT (AMPS)
1.0
4
5V
0.9
2
VGS = 4 V
0
0
4
6
8
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
2
10
0.8
0.7
– 50
0
50
100
TJ, JUNCTION TEMP (°C)
150
Figure 1. On Region Characteristics
Figure 2. Gate–Threshold Voltage Variation
With Temperature
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
4
TJ = – 55°C
I D, DRAIN CURRENT (AMPS)
3
0.5
VDS = 10 V
100°C
25°C
VGS = 10 V
0.4
TJ = 100°C
25°C
– 55°C
0.1
0.3
2
0.2
1
0
0
2
4
6
8
10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
0
0
2
ID, DRAIN CURRENT (AMPS)
4
Figure 3. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 4. On–Resistance versus Drain Current
0.5
TJ = 25°C
ID = 1 A
0.5
VGS = 10 V
ID = 1 A
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
4
6
8
10
12
14
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
16
0
– 50
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
150
Figure 5. On–Resistance versus
Gate–to–Source Voltage
Figure 6. On–Resistance versus Junction
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
3
MMFT1N10E
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on an ambient temperature of 25
°
C and a
maximum junction temperature of 150
°
C. Limitations for re-
petitive pulses at various ambient temperatures can be de-
termined by using the thermal response curves. Motorola
Application Note, AN569, “Transient Thermal Resistance–
General Data and Its Use” provides detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turn–on and turn–off of the devices for
switching times less than one microsecond.
1.0
r(t), EFFECTIVE THERMAL RESISTANCE
(NORMALIZED)
0.001
0.1
10
I D, DRAIN CURRENT (AMPS)
1
VGS = 20 V
SINGLE PULSE
TA = 25°C
20 ms
100 ms
0.1
1s
DC
500 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
0.01
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
D = 0.5
0.2
0.1
0.1
0.05
0.02
P(pk)
R
θJA
(t) = r(t) R
θJA
R
θJA
= 156°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TA = P(pk) R
θJA
(t)
0.01
0.01
SINGLE PULSE
0.001
1.0E–05
t1
t2
DUTY CYCLE, D = t1/t2
1.0E–01
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E+00
1.0E+01
Figure 8. Thermal Response
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source–drain
current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows the limita-
tions of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package,
and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; I FM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was at-
tained with dI S /dt of 400 A/µs.
4
Motorola TMOS Power MOSFET Transistor Device Data
MMFT1N10E
15 V
VGS
0
IFM
90%
IS
10%
ton
IRM
tfrr
VDS(pk)
VR
VDS
VdsL
MAX. CSOA
STRESS AREA
0.25 IRM
dlS/dt
trr
Vf
Figure 9. Commutating Waveforms
5
4.5
IS , SOURCE CURRENT (AMPS)
4
3.5
3
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
140
VGS
–
VR
+
IFM
+
20 V
–
IS
VDS
Li
dIS/dt
≤
400 A/µs
RGS
DUT
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VR = 80% OF RATED VDSS
VdsL = Vf + Li
⋅
dlS/dt
Figure 10. Commutating Safe Operating Area
(CSOA)
Figure 11. Commutating Safe Operating Area
Test Circuit
BVDSS
L
VDS
IL
VDD
t
RG
VDD
tP
t, (TIME)
IL(t)
Figure 12. Unclamped Inductive Switching
Test Circuit
Figure 13. Unclamped Inductive Switching
Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
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