MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MMDF3N04HD/D
Designer's
™
Data Sheet
Medium Power Surface Mount Products
MMDF3N04HD
Motorola Preferred Device
TMOS Dual N-Channel
Field Effect Transistor
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process. These
miniature surface mount MOSFETs feature ultra low RDS(on) and true
logic level performance. They are capable of withstanding high energy
in the avalanche and commutation modes and the drain–to–source
diode has a very low reverse recovery time. MiniMOS devices are
designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives. The avalanche energy is
specified to eliminate the guesswork in designs where inductive loads
are switched and offer additional safety margin against unexpected
G
voltage transients.
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
•
Logic Level Gate Drive — Can Be Driven by Logic ICs
•
Miniature SO–8 Surface Mount Package — Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed, With Soft Recovery
•
IDSS Specified at Elevated Temperature
•
Mounting Information for SO–8 Package Provided
•
Avalanche Energy Specified
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C (1)
Drain Current
— Continuous @ TA = 70°C (1)
Drain Current
— Pulsed Drain Current (4)
Total Power Dissipation @ TA = 25°C (1)
Linear Derating Factor (1)
Total Power Dissipation @ TA = 25°C (2)
Linear Derating Factor (2)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 4.0 mH, VDS = 40 Vdc)
DUAL TMOS
POWER MOSFET
3.4 AMPERES
40 VOLTS
RDS(on) = 0.080 OHM
™
D
CASE 751–05, Style 14
SO–8
S
Source–1
Gate–1
Source–2
Gate–2
1
2
3
4
8
7
6
5
Drain–1
Drain–1
Drain–2
Drain–2
Top View
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
PD
TJ, Tstg
EAS
Value
40
40
±
20
3.4
3.0
40
2.0
16
1.39
11.11
– 55 to 150
162
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
mW/°C
Watts
mW/°C
°C
mJ
THERMAL RESISTANCE
Rating
Symbol
Typ.
—
—
Max.
62.5
90
Unit
°C/W
Thermal Resistance — Junction to Ambient, PCB Mount (1)
R
θJA
R
θJA
— Junction to Ambient, PCB Mount (2)
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 10 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 10 V, @ Steady State)
DEVICE MARKING
D3N04H
Device
MMDF3N04HDR2
ORDERING INFORMATION
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
2500 units
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices
are Motorola recommended choices for future use and best overall value.
HDTMOS, MiniMOS, and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Micro–8 is a registered trademark of International Rectifier. Thermal Clad is a trademark of the Berquist Company.
REV 1
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MMDF3N04HD
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 40 Vdc, VGS = 0 Vdc)
(VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 3.4 Adc)
(VGS = 4.5 Vdc, ID = 1.7 Adc)
(Cpk
≥
2.0)
(1) (3)
VGS(th)
1.0
—
(Cpk
≥
2.0)
(1) (3)
RDS(on)
—
—
(1)
gFS
2.0
55
79
4.5
80
100
—
Mhos
2.0
4.9
3.0
—
Vdc
mV/°C
mΩ
(Cpk
≥
2.0)
(1) (3)
V(BR)DSS
40
—
IDSS
—
—
IGSS
—
0.015
0.15
0.013
2.5
10
500
nAdc
—
4.3
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
Ciss
(VDS = 32 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
Crss
—
—
—
450
130
32
900
230
96
pF
td(on)
(VDD = 20 Vdc, ID = 3.4 Adc,
VGS = 10 Vdc, RG = 6
Ω)
(1)
tr
td(off)
tf
td(on)
(VDD = 20 Vdc, ID = 1.7 Adc,
VGS = 4.5 Vdc, RG = 6
Ω)
(1)
tr
td(off)
tf
QT
(VDS = 40 Vdc, ID = 3.4 Adc,
VGS = 10 Vdc) (1)
Q1
Q2
Q3
—
—
—
—
—
—
—
—
—
—
—
—
9.0
15
28
19
13
77
17
20
13.9
2.1
3.7
5.4
18
30
56
38
26
144
34
40
28
—
—
—
ns
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 3.4 Adc, VGS = 0 Vdc) (1)
(IS = 3.4 Adc, VGS = 0 Vdc, TJ = 125°C)
VSD
—
—
trr
(IS = 3.4 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs) (1)
Reverse Recovery Storage Charge
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk =
3 x SIGMA
(4) Repetitive rating; pulse width limited by maximum junction temperature.
ta
tb
QRR
—
—
—
—
0.87
0.8
27
20
7.0
0.03
1.5
—
—
—
—
—
µC
ns
Vdc
Reverse Recovery Time
2
Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N04HD
TYPICAL ELECTRICAL CHARACTERISTICS
6
I D , DRAIN CURRENT (AMPS)
5
4
3
2
1
0
2.7 V
VGS =
10 V
3.9 V
4.5 V
4.3 V
4.1 V
6
TJ = 25°C
3.7 V
I D , DRAIN CURRENT (AMPS)
5
4
3
2
1
0
1.5
VDS
≥
10 V
TJ = 25°C
3.5 V
100°C
25°C
TJ = –55°C
3.3 V
3.1 V
2.9 V
1.4
1.6
1.8
2
0
0.2
0.4
0.6
0.8
1
1.2
2
2.5
3
3.5
4
4.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.6
0.5
0.4
0.3
0.2
0.1
0
2
3
4
5
6
7
8
9
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
ID = 3.4 A
TJ = 25°C
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.1
0.095
0.09
0.085
0.08
0.075
0.07
0.065
0.06
0.055
0.05
0
1
2
3
4
5
6
ID, DRAIN CURRENT (AMPS)
10 V
VGS = 4.5
TJ = 25°C
Figure 3. On–Resistance versus
Gate–to–Source Voltage
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.0
VGS = 10 V
ID = 3.4 A
I DSS , LEAKAGE (nA)
1.5
100
VGS = 0 V
TJ = 125°C
10
100°C
1.0
1
25°C
0.5
0
– 50
– 25
0
25
50
75
100
125
150
0.1
0
5
10
15
20
25
30
35
40
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation
with Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MMDF3N04HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
1200
VDS = 0 V
Ciss
VGS = 0 V
TJ = 25°C
900
C, CAPACITANCE (pF)
600
Crss
Ciss
300
Coss
Crss
0
10
5
VGS
0
VDS
5
10
15
20
25
30
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N04HD
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
12
QT
40
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1000
VDD = 20 V
ID = 3.4 A
VGS = 10 V
TJ = 25°C
9
VDS
30
100
t, TIME (ns)
6
VGS
20
10
3
Q1
Q3
Q2
ID = 3.4 A
TJ = 25°C
td(off)
tf
tr
td(on)
10
0
0
4
8
Qg, TOTAL GATE CHARGE (nC)
12
0
16
1
1
10
RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short t rr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
3.5
3.0
IS, SOURCE CURRENT (AMPS)
2.5
2.0
1.5
1.0
0.5
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
0.9
di/dts. The diode’s negative di/dt during ta is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re-
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
TJ = 25°C
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
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