Standard Products
MIP7365
64-Bit Superscaler Microprocessor
January 11, 2007
FEATURES
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Upscreened PMC-Sierra RM7065C
Military and Industrial Grades Available
Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level
price/performance
o 450MHz operating frequency
High-performance system interface
o Multiplexed address/data bus (SysAD) supports 2.5V, 3.3V I/O logic
o Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
o Support for 64-bit or 32-bit external agents
Integrated primary and secondary caches
o All are 4-way set associative with 32-byte line size
o 16-Kbytes instruction, 16-Kbytes data, 256-Kbytes on-chip secondary
o Per line cache locking in primaries and secondary
o Fast Packet Cache™ increases system efficiency in networking applications
High-performance floating-point unit — 1600MFLOPS maximum
o Single cycle repeat rate for common single-precision operations and some double-precision operations
o Single cycle repeat rate for single-precision combined multiply-add operations
o Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
MIPS IV superset instruction set architecture
o Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
o Single-cycle floating-point multiply-add
Integrated memory management unit
o Fully associative joint TLB (shared by I and D translations)
o 64/48 dual entries map 128/96 pages
o Variable page size
Embedded application enhancements
o Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply
instruction (MUL)
o I&D Test/Break-point (Watch) registers for emulation & debug
o Performance counter for system and software tuning & debug
o Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software
Fully static CMOS design with dynamic power down logic
216-EPad LQFP 24x24mm are pin compatible with the RM7965 and RM5261A EPad™ products
NOTE: 216-Enhanced Pad package, EPad MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra
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SCD7365 Rev B
BLOCK DIAGRAM
SCD7365 Rev B 1/11/07
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DESCRIPTION
The MIP7365 Microprocessor is a highly integrated symmetric superscalar microprocessor capable of issuing two
instructions each processor cycle. It has two highperformance 64-bit integer units as well as a high-throughput, fully
pipelined 64-bit floating point unit.
The MIP7365 integrates 16 Kbytes 4-way set associative instruction and data caches along with an integrated 256 Kbytes
4-way set associative secondary cache. The primary data and secondary caches are write-back and non-blocking.
The memory management unit contains a 64/48-entry fully associative TLB and a 64-bit system interface supporting
multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts.
The MIP7365 is available in a 216-EPad LQFP package. The 216-EPad package is pin compatible with previous RM7965
and the RM5261A ExposedPad products.
The MIP7365 ideally suits high-end embedded control applications such as internetworking, high-performance image
manipulation, high-speed printing, and 3-D visualization. The MIP7365 is also applicable to the low end workstation
market where its balanced integer and floating-point performance provides outstanding price/performance.
For additional Detail Information regarding the operation of the PMC-Sierra see the latest PMC-Sierra datasheet for the RM7065C
Family Microprocessors Data Sheet, Issue No. 5: August 2006; Document No. PMC-2021816, Issue 5
SCD7365 Rev B 1/11/07
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PIN DESCRIPTIONS
The following is a list of control, data, clock, interrupt, and miscellaneous pins of MIP7365.
System Interface
PIN NAME
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
TYPE
Input
Output
Input
Input
Input
DESCRIPTION
External request
Signals that the external agent is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the bus and a valid
command or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
Processor Request
When asserted this signal requests that control of the system interface be returned to the
processor. This is enabled by Mode Bit 26
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the processor that it has been
granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor when it is about to return a
memory reference out of order; i.e., of two outstanding memory references, the data for the
second reference is being returned ahead of the data for the first reference. In order that the
processor will have time to switch the address to the tertiary cache, this signal must be asserted
a minimum of two cycles prior to the data itself being presented. Note that this signal works as
a toggle; i.e., for each cycle that it is held asserted the order of return is reversed. By default,
anytime the processor issues a second read it is assumed that the reads will be returned in
order; i.e., no action is required if the reads are indeed returned in order. This is enabled by
Mode Bit 26.
Read Type
During the address cycle of a read request, RdType indicates whether the read request is an
instruction read or a data read.
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.
System Command/Data Identifier Bus Parity
For the MIP7365, unused on input and zero on output.
ValidOut*
Output
PRqst*
Output
PAck*
Input
RspSwap*
Input
RdType
Output
SysAD[63:0]
SysADC[7:0]
SysCmd[8:0]
Input/Output
Input/Output
Input/Output
SysCmdP
Input/Output
SCD7365 Rev B 1/11/07
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Clock/Control Interface
PIN NAME
Master Clock
TYPE
Input
DESCRIPTION
System clock
Master clock input used as the system interface reference clock. All output timings are relative
to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the
factor selected during boot initialization.
Power Supply
PIN NAME
VccInt
VccIO
VccP
TYPE
Input
Input
Input
DESCRIPTION
Power supply for core.
Power supply for I/O.
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter
circuit.
Power supply used for JTAG.
Ground Return.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
VccJ
Vss
VssP
Input
Input
Input
Interrupt Interface
PIN NAME
INT[9:0]*
NMI*
TYPE
Input
Input
DESCRIPTION
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register (bit 6 in R5000
compatibility mode).
JTAG Interface
PIN NAME
JTDI
JTCK
JTDO
JTMS
JTRST*
TYPE
Input
Input
Output
Input
Input
DESCRIPTION
JTAG data in
JTAG clock input
JTAG data out
JTAG command
JTAG reset.
Notes:
1. The
JTRST*
input was added to the RM70xxC and RM79xx CPUs to directly control the reset to the JTAG state machine. JTAG boundary
scan test equipment must be able to drive
JTRST*
high to allow JTAG boundary scan operation.
2. The
JTRST*
input must be connected to GND (Vss) through a 220
Ω
to 1 K
Ω
pull-down resistor to force the JTAG state machine into the
reset state to allow normal operation (JTAG boundary scan mode disabled).
3. The JTAG interface electrical characteristics are dependent on the
VccJ
level chosen (2.5 V or 3.3 V).
SCD7365 Rev B 1/11/07
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