v1.0
Automotive ProASIC3 Flash Family FPGAs
Features and Benefits
High-Temperature AEC-Q100–Qualified Devices
• Grade 2 105°C T
A
(115°C T
J
)
• Grade 1 125°C T
A
(135°C T
J
)
• PPAP Documentation
®
Low Power
• 1.5 V Core Voltage
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Firm-Error Immune
• Only Automotive FPGAs to Offer Firm-Error Immunity
• Can Be Used without Configuration Upset Risk
Advanced I/O
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and A3P1000)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the Automotive ProASIC
®
3
Family
High Capacity
• 60 k to 1 M System Gates
• Up to 144 kbits of SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Automotive Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interface
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 350 MHz)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents (anti-tampering)
SRAMs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
Automotive ProASIC3 Product Family
ProASIC3 Devices
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals*
I/O Banks
Maximum User I/Os
Package Pins
VQFP
FBGA
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
FG144
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
VQ100
FG144
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
VQ100
FG144, FG256
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
FG144, FG256, FG484
Note:
*Six chip-wide (main) globals and three additional global networks in each quadrant are available.
January 2008
© 2008 Actel Corporation
I
I/Os Per Package
ProASIC3 Devices
A3P060
A3P125
A3P250
I/O Type
Differential I/O Pairs
Differential I/O Pairs
–
25
44
74
Single-Ended I/O
2
–
97
177
300
Single-Ended I/O
2
A3P1000
Single-Ended I/O
Package
VQ100
FG144
FG256
FG484
Notes:
71
96
–
–
71
97
–
–
Single-Ended I/O
68
97
157
–
13
24
38
–
1. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3 Flash Family FPGAs
handbook to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of available single-ended I/Os by two.
3. FG256 and FG484 are footprint-compatible packages.
Automotive ProASIC3 Ordering Information
A3P1000
_
1
FG
G
144
T
Application (Temperature Range)
T = Grade 2 and Grade 1 AECQ100
Grade 2 = 105°C T
A
and 115°C T
J
Grade 1 = 125°C T
A
and 135°C T
J
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
Part Number
Automotive ProASIC3 Devices
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P1000 = 1,000,000 System Gates
Note:
Minimum order quantities apply. Contact your local Actel sales office for details.
II
v1.0
Automotive ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
VQ100
FG144
FG256
FG484
Notes:
1. C = Commercial temperature range: 0°C to 70°C
2. I = Industrial temperature range: –40°C to 85°C
3. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C T
A
and 115°C T
J
Grade 1 = 125°C T
A
and 135°C T
J
4. Specifications for Commercial and Industrial grade devices can be found in the
ProASIC3 Flash Family FPGAs
handbook.
A3P060
C, I, T
C, I, T
–
–
A3P125
C, I, T
C, I, T
–
–
A3P250
C, I, T
C, I, T
C, I, T
–
A3P1000
–
C, I, T
C, I, T
C, I, T
Speed Grade and Temperature Grade Matrix
Temperature Grade
T (Grade 1 and Grade 2), Commercial, Industrial
Notes:
1. T = Automotive temperature range: Grade 2 and Grade 1 AEC-Q100
Grade 2 = 105°C T
A
and 115°C T
J
Grade 1 = 125°C T
A
and 135°C T
J
2. Specifications for Commercial and Industrial grade devices can be found in the
ProASIC3 Flash Family FPGAs
handbook.
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
Std.
–1
✓
✓
v1.0
III
1 – Automotive ProASIC3 Device Family Overview
General Description
Automotive ProASIC3 nonvolatile flash technology gives automotive system designers the
advantage of a secure, low-power, single-chip solution that is live at power-up (LAPU). Automotive
ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems using existing ASIC or FPGA design flows
and tools.
Automotive ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM
storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL).
Automotive ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of
SRAM and up to 300 user I/Os.
Automotive ProASIC3 devices are the only firm-error-immune automotive grade FPGAs. Firm-error
immunity makes them ideally suited for demanding applications in powertrain, safety, and
telematics-based subsystems, where firm-error failure is not an option.
Firm errors in SRAM-based FPGAs can result in high defect levels in field-deployed systems. These
unavoidable defects must be considered separately from standard defects and failure mechanisms
when looking at overall system quality and reliability.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based Automotive ProASIC3 devices allow all functionality to be live at
power-up; no external boot PROM is required. On-board security mechanisms prevent access to all
the programming information and enable secure remote updates of the FPGA logic. Flash-based
FPGAs are LAPU Class 0 devices, offering the lowest available power in a single-chip device and
providing firm-error immunity. The Automotive ProASIC3 family device architecture mitigates the
need for ASIC migration at high user volumes. This makes the Automotive ProASIC3 family a cost-
effective ASIC replacement solution, especially for automotive applications.
Security
The nonvolatile, flash-based Automotive ProASIC3 devices do not require a boot PROM, so there is
no vulnerable external bitstream that can be easily copied. Automotive ProASIC3 devices
incorporate FlashLock, which provides a unique combination of reprogrammability and design
security without external overhead, advantages that only an FPGA with nonvolatile flash
programming can offer.
Automotive ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to secure
programmed intellectual property and configuration data. In addition, all FlashROM data in
Automotive ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-
128 (FIPS192) bit block cipher encryption standard. The AES was adopted by the National Institute
of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. Automotive
ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them
the most comprehensive programmable logic device security solution available today. Automotive
ProASIC3 devices with AES-based security allow for secure, remote field updates over public
networks such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. The contents of a programmed Automotive ProASIC3
device cannot be read back, although secure design verification is possible. Additionally, security
features of Automotive ProASIC3 devices provide anti-tampering protection.
Security, built into the FPGA fabric, is an inherent component of the Automotive ProASIC3 family.
The flash cells are located beneath seven metal layers, and many device design and layout
v1.0
1-1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
