v1.0
ProASIC3E Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
®
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
®
3E Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable
Phase-Shift,
Multiply/Divide,
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 200 MHz)
Delay
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
®
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
High-Performance Routing Hierarchy
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
ARM Processor Support in ProASIC3E FPGAs
Pro (Professional) I/O
• 700 Mbps DDR, LVDS-Capable I/Os
Table 1-1 •
ProASIC3E Product Family
ProASIC3E Devices
Cortex-M1 Devices
1
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
CCCs with Integrated PLLs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
PQFP
FBGA
3
2
A3PE600
600 k
13,824
108
24
1k
Yes
6
18
8
270
PQ208
FG256, FG484
A3PE1500
M1A3PE1500
1.5 M
38,400
270
60
1k
Yes
6
18
8
444
PQ208
FG484, FG676
A3PE3000
M1A3PE3000
3M
75,264
504
112
1k
Yes
6
18
8
620
PQ208
FG324
,
FG484, FG896
Notes:
1. Refer to the
Cortex-M1
product brief for more information.
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the
ProASIC3 Flash Family FPGAs
handbook.
March 2008
© 2008 Actel Corporation
I
I/Os Per Package
1
ProASIC3E Devices
Cortex-M1 Devices
2
A3PE600
A3PE1500
3
M1A3PE1500
I/O Types
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
65
–
110
168
–
310
Single-Ended I/O
1
Single-Ended I/O
1
Single-Ended I/O
1
147
–
221
341
–
620
A3PE3000
3
M1A3PE3000
Package
PQ208
FG256
FG324
FG484
FG676
FG896
Notes:
147
165
–
270
–
–
65
79
–
135
–
–
147
–
–
280
444
–
65
–
–
139
222
–
1. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3E Flash Family FPGAs
handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per
minibank (group of I/Os).
6. "G" indicates RoHS-compliant packages. Refer to the
"ProASIC3E Ordering Information" on page III
for the location of
the "G" in the part number.
II
v1.0
ProASIC3E Flash Family FPGAs
ProASIC3E Ordering Information
A3PE3000 _
1
FG
G
896
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (–40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant (Green) Packaging
Package Type
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F =
Blank =
1=
2=
20% Slower than Standard*
Standard
15% Faster than Standard
25% Faster than Standard
Part Number
ProASIC3E Devices
A3PE600 = 600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
ProASIC3E Devices with Cortex-M1
M1A3PE1500 = 1,500,000 System Gates
M1A3PE3000 = 3,000,000 System Gates
*
The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided
for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will
be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
v1.0
III
Temperature Grade Offerings
Package
Cortex-M1 Devices
PQ208
FG256
FG324
FG484
FG676
FG896
C, I
C, I
–
C, I
–
–
A3PE600
A3PE1500
M1A3PE1500
C, I
–
–
C, I
C, I
–
A3PE3000
M1A3PE3000
C, I
–
C, I
C, I
–
C, I
Note:
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature
3. I = Industrial temperature range: –40°C to 85°C ambient temperature
References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start
with M1 (Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
–F
1
Std.
–1
–2
✓
–
✓
✓
✓
✓
✓
✓
IV
v1.0
1 – ProASIC3E Device Family Overview
General Description
ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and
features beyond those of the ProASIC
PLUS®
family. Nonvolatile flash technology gives ProASIC3E
devices the advantage of being a secure, low-power, single-chip solution that is live at power-up
(LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices
have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and
up to 620 user I/Os.
Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have
Actel ordering numbers that begin with M1A3PE.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property (IP) cannot be compromised or
copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E
family device architecture mitigates the need for ASIC migration at higher user volumes. This
makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications
in the consumer, networking/ communications, computing, and avionics markets.
Security
The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock,
which provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices
can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. The AES standard was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in
AES decryption engine and a flash-based AES key that make them the most comprehensive
programmable logic device security solution available today. ProASIC3E devices with AES-based
security allow for secure, remote field updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP
thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure
design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash
cells are located beneath seven metal layers, and many device design and layout techniques have
been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and
AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your
v1.0
1-1
FPGA/CPLD
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