512K x 32 SRAM MODULE
PUMA 2/77S16000/A - 020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
Description
16,777,216 bit CMOS High Speed Static RAM
Available in PGA (PUMA 2 ) and Gullwing (PUMA 77)
Features
footprints, the PUMA **S16000 is a 16 MBit SRAM • 16MBit Fast SRAM Module.
module user configurable as 512K x 32, 1M x 16 or 2M • Fast Access times of 20/25/35ns.
x 8. The device is available with fast access times of
• Configurable as 8 / 16 / 32 bit wide output.
20,25 and 30ns. A low power standby and Data
Retention mode is available. The device may be • Operating Power 2130 / 2800 / 4150 mW (max).
Standby CMOS 220mW (max).
screened in accordance with MIL-STD-883.
• Low voltage data retention.
• Single 5V±10% Power supply.
• TTL compatible inputs and outputs.
• May be screened in accordance with MIL-STD-883.
• PUMA 2 - 66 pin ceramic PGA
• PUMA77 - 68 pin ceramic Gullwing
Block Diagram
PUMA 2S16000 and 77S16000A
A0~A18
OE
WE4
WE3
WE2
WE1
512K x 8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
Block Diagram
PUMA 77S16000
A0~A18
OE
WE
512K x 8
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
Pin Functions
A0~A18
CS1~4
WE1~4
V
CC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~D31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
ISSUE 4.2 : November 1998
PUMA 2/77S16000/A - 020/025/35
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
ss (2)
Power Dissipation
Storage Temperature
Notes
V
T
-0.5V to +7.0
P
D
4
T
STG
-55 to +150
V
W
°
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
(2) Pulse width:- 3.0V for less than 10ns.
Recommended Operating Conditions
Parameter
Symbol
min
Supply Voltage
V
CC
4.5
Input High Voltage
V
IH
2.2
Input Low Voltage
V
IL
-0.5
Operating Temperature
T
A
0
T
AI
-40
T
AM
-55
typ
5.0
-
-
-
-
-
max
5.5
V
CC
+0.5
0.8
70
85
125
units
V
V
V
°
C
°
C (Suffix
I)
°
C (Suffix
M, MB)
DC Electrical Characteristics
(V
CC
=5V±10%,T
A
=-55°C to +125°C)
Parameter
Symbol Test Condition
I
LI1
I
LI2
I
LO
I
CC32
I
CC16
I
CC8
I
SB
I
SB1
V
OL
V
OH
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
CS
(2)
= V
IH
or OE = V
IH
, V
I/O
= 0V to V
CC
WE
(2)
= V
IL
CS
(2)
=
V
IL
, Minumum cycle, I
I/O
= 0mA
WE
(2)
=V
IL
or WE
(2)
=OE=V
IH
, 100% duty.
As above
As above
CS
(2)
= V
IH ,
V
CC
=5.5V
CS
(2)
≥
V
CC
-0.2V, 0.2V
≥
V
IN
≥
V
CC
-0.2V
I
OL
= 8.0 mA
I
OH
= -4.0 mA
min
-8
-2
-8
typ
(1)
-
-
-
max Unit
8
2
8
µA
µA
µA
Input Leakage Current Address,OE
WE, CS
Output Leakage Current
Average Supply Current
32 bit
16 bit
8 bit
Standby Supply Current TTL levels
CMOS levels
Output Voltage Low
Output Voltage High
-
-
-
-
-
-
2.4
-
-
-
-
-
-
-
720
480
360
240
40
0.4
-
mA
mA
mA
mA
mA
V
V
Notes: (1) Typical values are at V
CC
=5.0V,T
A
=25
°
C and specified loading.
(2) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated
simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
2
PUMA 2/77S16000 - 020/025/35
ISSUE 4.2 : November 1998
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Note: These parameters are calculated and not measured.
Parameter
Input Capacitance Address, OE
WE1~4, CS1~4
I/O Capacitance
D0~31
Symbol
C
IN1
C
IN2
C
I/O
Test Condition
V
IN
=0V
V
IN
=0V
V
I/O
=0V
typ
-
-
-
max Unit
34
6
42
pF
pF
pF (8 bit mode)
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
device.
Mode
Not Selected
Output Disable
Read
Write
1 = V
IH
,
0 = V
IL
,
X = Don't Care
CS
1
0
0
0
OE
X
1
0
X
WE
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
CC
I
CC
I
CC
I/O Pin
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
Read cycle
Write Cycle
Note: CS above is accessed through CS1~4 and WE is accessed through WE1~4. For correct operation, CS1~ 4 and
WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55°C to +125
o
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Symbol Test Condition
V
DR
I
CCDR
CS1~4
≥
V
CC
-0.2V
V
CC
= 3.0V, CS1~4
≥
V
CC
-0.2V,
0.2V
≥
V
IN
≥
V
CC
-0.2V
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
-
-
-
-
max
5.5
28
-
-
Unit
V
mA
ns
ms
Chip Deselect to Data Retention t
CDR
Operation Recovery Time
t
R
AC Test Conditions
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*V
cc
=5V±10%
*PUMA module is tested in 32 bit mode.
Output Load
I/O Pin
166
Ω
1.76V
30pF
3
ISSUE 4.2 : November 1998
PUMA 2/77S16000/A - 020/025/35
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
020
min max
20
-
-
-
5
5
5
-
0
-
20
20
10
-
-
-
10
10
025
min max
25
-
-
-
5
5
0
0
0
-
25
25
15
-
-
-
10
10
35
min max
35
-
-
-
5
5
0
0
0
-
35
35
15
-
-
-
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
(3)
Output Disable to Output in High Z
(3)
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
020
Symbol min max
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
20
15
15
0
15
0
0
10
0
5
-
-
-
-
-
10
-
-
-
025
min max
25
15
15
0
15
0
0
10
0
5
-
-
-
-
-
-
10
-
-
-
35
min max Unit
35
15
15
0
15
0
0
10
0
5
-
-
-
-
-
-
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 2/77S16000 - 020/025/35
ISSUE 4.2 : November 1998
Read Cycle Timing Waveform
(1,2)
t
Address
RC
t
AA
OE
t
OE
t
OLZ
CS1~4
t
OH
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
High-Z
D0~31
Notes:
(1) During the Read Cycle, WE is high for the module.
(2) Address valid prior to or coincident with CS transition Low.
Data Valid
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
A0~A18
OE
t
AS(3)
t
AW
t
CW(4)
(6)
t
WR
(2)
CS1~4
t
WP(1)
WE1~4
t
OHZ(3,9)
High-Z
t
DW
High-Z
t
OW
t
DH
D0~31out
D0~31in
5
FPGA/CPLD
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