High Performance
32K
×
9
CMOS SRAM
32K
×
9 CMOS SRAM (Common I/O)
FEATURES
• Organization: 32,768 words × 9 bits
• High speed
• 2.0V data retention (L version)
• Equal access and cycle times
AS7C259
AS7C259L
– 12/15/20/25/35 ns address access time
– 3/4/5/6/8 ns output enable access time
• Low power consumption
• Easy memory expansion with CE1, CE2, and OE inputs
• TTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
– Active:
– Standby:
633 mW max (10 ns cycle)
11 mW max, CMOS I/O
2.75 mW max, CMOS I/O, L version
– 300 mil PDIP and SOJ
• ESD protection > 2000 volts
• Latch-up current > 200 mA
– Very low DC component in active power
LOGIC BLOCK DIAGRAM
PIN ARRANGEMENT
DIP, SOJ
Vcc
GND
INPUT BUFFER
NC
NC
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A14
CE2
WE
A13
A9
A10
A11
OE
A12
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A0
A1
A2
A3
A4
A5
A6
A14
ROW DECODER
128 × 64 × 9
ARRAY
(294,912)
SENSE AMP
I/O0
WE
COLUMN DECODER
CONTROL
CIRCUIT
OE
CE1
CE2
A A A A A A A
7 8 9 10 11 12 13
AS7C259-01
AS7C259
I/O8
AS7C259-02
SELECTION GUIDE
7C259-12
Maximum Address Access Time
Maximum Output Enable Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
L
12
4
115
2.0
0.5
7C259-15
15
4
110
2.0
0.5
7C259-20
20
5
100
2.0
0.5
7C259-25
25
6
90
2.0
0.5
7C259-35
35
8
80
2.0
0.5
Unit
ns
ns
mA
mA
mA
ALLIANCE SEMICONDUCTOR
AS7C259
AS7C259L
FUNCTIONAL DESCRIPTION
The AS7C259 is a high performance CMOS 294,912-bit
Static Random Access Memory (SRAM) organized as
32,768 words × 9 bits. It is designed for memory applica-
tions where fast data access, low power, and simple interfac-
ing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of
12/15/20/25/35 ns with output enable access times (t
OE
) of
3/4/5/6/8 ns are ideal for high performance applications.
Active high and low chip enables (CE1, CE2) permit easy
memory expansion with multiple-bank memory systems.
When CE1 is HIGH or CE2 is LOW the device enters
standby mode. The standard AS7C259 is guaranteed not to
exceed 11 mW power consumption in standby mode; the L
version is guaranteed not to exceed 1.1 mW. The L version
also offers 2.0V data retention.
A write cycle is accomplished by asserting write enable
(WE) and both chip enables (CE1, CE2). Data on the input
pins I/O0-I/O7 is written on the rising edge of WE (write
cycle 1) or the active-to-inactive edge of CE1 or CE2 (write
cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with
output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable
(OE) and both chip enables (CE1, CE2), with write enable
(WE) HIGH. The chip drives I/O pins with the data word
referenced by the input address. When either chip enable or
output enable is inactive, or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and opera-
tion is from a single 5V supply. The AS7C259 is packaged
in common industry standard packages.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to GND
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
V
t
P
D
T
stg
T
bias
Min
–0.5
–
–55
–10
Max
+7.0
1.0
+150
+85
Unit
V
W
o
C
o
C
–
20
mA
DC Output Current
I
out
NOTE:
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
.
TRUTH TABLE
CE1
H
X
L
L
CE2
X
L
H
H
WE
X
X
H
H
OE
X
X
H
L
X
Data
High Z
High Z
High Z
D
out
D
in
Mode
Standby (I
SB
, I
SB1
)
Standby (I
SB
, I
SB1
)
Output Disable
Read
Write
L
H
L
Key:
X = Don’t Care, L = LOW, H = HIGH
2
AS7C259
AS7C259L
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input Voltage
* V
IL
min = –3.0V for pulse width less than t
RC
/2.
Symbol
V
CC
GND
V
IH
V
IL
Min
4.5
0.0
2.2
–0.5
*
Typ
5.0
0.0
–
–
(T
a
= 0°C to +70°C)
Max
5.5
0.0
V
CC
+1.0
0.8
Unit
V
V
V
V
DC OPERATING CHARACTERISTICS
1
Parameter
Input Leakage
Current
Output Leakage
Current
Operating Power
Supply Current
Standby
Power Supply
Current
Symbol Test Conditions
|
I
LI
|
V
CC
= Max,
V
in
= GND to V
CC
-12
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-15
-20
-25
-35
Unit
µA
µA
mA
mA
mA
mA
mA
mA
V
V
Min Max Min Max Min Max Min Max Min Max
–
1
–
1
–
1
–
1
–
1
CE1 = V
IH
or
CE2 = V
IL
,
|
I
LO
|
V
CC
= Max,
V
out
= GND to V
CC
I
CC
I
SB
I
SB1
V
OL
CE1 = V
IL
, CE2 = V
IH
,
f
=
f
max,
I
out
= 0 mA
CE1 = V
IH
or
CE2 = V
IL
,
f
=
f
max
CE1
≥
V
CC
–0.2V
or
CE2
≤0.2V,
V
in
≤
0.2V
or
V
in
≥
V
CC
–0.2V,
f
=0
I
OL
= 8 mA, V
CC
= Min
L
L
–
–
–
–
–
–
L
–
–
2.4
1
115
110
40
35
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
2.4
1
110
105
30
25
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
2.4
1
100
95
30
25
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
2.4
1
90
85
25
20
2.0
0.5
0.4
–
–
–
–
–
–
–
–
–
2.4
1
80
75
25
20
2.0
0.5
0.4
–
V
OH
I
OH
= –4 mA, V
CC
= Min
Shaded areas contain advance information.
Output Voltage
CAPACITANCE
2
Parameter
Symbol
C
IN
C
I/O
Signals
(f = 1 MHz, T
a
= room temperature, V
CC
= 5V)
Test Conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
Input Capacitance
I/O Capacitance
A, CE1, CE2, WE, OE
I/O
3
AS7C259
AS7C259L
READ CYCLE
3, 9, 12
Parameter
Read Cycle Time
Address Access Time
Chip Enable (CE1) Access Time
Chip Enable (CE2) Access Time
Output Enable (OE) Access Time
Output Hold from Address Change
CE1 LOW to Output in Low Z
CE2 HIGH to Output in Low Z
CE1 HIGH to Output in High Z
CE2 LOW to Output in High Z
OE LOW to Output in Low Z
OE HIGH to Output in High Z
Power Up Time
Power Down Time
Shaded areas contain advance information.
Symbol
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
PU
t
PD
-12
12
–
–
–
–
3
3
3
–
–
0
–
0
–
–
12
12
12
3
–
–
–
3
3
–
3
–
12
15
–
–
–
–
3
3
3
–
–
0
–
0
–
-15
–
15
15
15
4
–
–
–
4
4
–
4
–
15
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-20
20
–
–
–
–
3
3
3
–
–
0
–
0
–
–
20
20
20
5
–
–
–
5
5
–
5
–
20
25
–
–
–
–
3
3
3
–
–
0
–
0
–
-25
–
25
25
25
6
–
–
–
6
6
–
6
–
25
35
–
–
–
–
3
3
3
–
–
0
–
0
–
-35
–
35
35
35
8
–
–
–
8
8
–
8
–
35
Min Max Min Max Min Max Min Max Min Max
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
3
3, 12
3, 12
TIMING WAVEFORM OF READ CYCLE 1
3, 6, 7, 9, 12
t
RC
Address
t
AA
D
out
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA
(Address Controlled)
t
OH
Data Valid
AS7C259-03
TIMING WAVEFORM OF READ CYCLE 2
3, 6, 8, 9, 12
t
RC1
CE1
CE2
AAAAAAAAAAAAAAAAAAAAAAAAA
OE
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
(CE1 and CE2 Controlled)
t
OE
t
OLZ
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
OHZ
t
ACE1
, t
ACE2
D
out
t
CLZ1
, t
CLZ2
Current
Supply
t
PU
50%
Data Valid
t
CHZ1
, t
CHZ2
t
PD
50%
I
CC
I
SB
AS7C259-04
4
AS7C259
AS7C259L
WRITE CYCLE
11, 12
Parameter
Write Cycle Time
Chip Enable (CE1) to Write End
Chip Enable (CE2) to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Address Hold From End of Write
Data Valid to Write End
Data Hold Time
Write Enable to Output in High Z
Output Active From Write End
Shaded areas contain advance information.
Symbol
t
WC
t
CW1
t
CW2
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
-12
12
10
10
10
0
8
0
6
0
–
3
–
–
–
–
–
–
–
–
–
5
–
15
12
12
12
0
9
0
8
0
–
3
-15
–
–
–
–
–
–
–
–
–
5
–
(V
CC
= 5V±10%, GND = 0V, T
a
= 0°C to +70°C)
-20
20
12
12
12
0
12
0
10
0
–
3
–
–
–
–
–
–
–
–
–
5
–
20
15
15
15
0
15
0
10
0
–
3
-25
–
–
–
–
–
–
–
–
–
5
–
30
20
20
20
0
17
0
15
0
–
3
-35
–
–
–
–
–
–
–
–
–
5
–
Min Max Min Max Min Max Min Max Min Max
Unit
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
12
12
12
TIMING WAVEFORM OF WRITE CYCLE 1
10, 11, 12
t
WC
t
AW
Address
WE
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
(WE Controlled)
t
AH
t
WP
t
DW
Data Valid
t
WZ
t
OW
AS7C259-05
t
AS
D
in
t
DH
D
out
TIMING WAVEFORM OF WRITE CYCLE 2
10, 11, 12
t
WC
t
AW
Address
t
AS
CE1
CE2
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
(CE1 and CE2 Controlled)
t
AH
t
CW1,
t
CW2
t
WP
t
WZ
t
DW
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
t
DH
D
in
D
out
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Data Valid
AS7C259-06
5
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