The AS5LC2M16 is a low-power single transistor (1T) CMOS 33,554,432-bit Pseudo Static Random Access Memory (PSRAM)
device organized as 2,097,152 × 16 bits. It is designed for memory applications where slow data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 55/70/85 ns are ideal for low-power applications. Active high and low
chip selects (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
The device can also be put into standby mode when deselected (CS1 is high or CS2 is low, or UB and LB are high). The input/
output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS1 is high or CS2 is low, or UB and
LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or
CS2 is high and WE Low).
Writing to the device is accomplished by taking Chip Selects CS1 Low, CS2 High and Write Select (WE) input Low. If Byte Low
Select (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0
through A20). If Byte High Select (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location spec-
ified on the address pins (A0 through A20). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Select CS1 Low, CS2 High and Output Enable (OE) Low while forcing
the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to V
SS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with V
CC
applied
DC output current (low)
Symbol
V
tIN
V
tI/O
P
D
T
stg
T
bias
I
OUT
Min
–0.5
–0.5
–
–65
–55
–
Max
V
CC
+ 0.5
V
CC
+ 0.5
1.0
+150
+125
20
Unit
V
V
W
°
C
°
C
mA
Note: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2/15/02; V.0.9.6
Alliance Semiconductor
P. 2 of 10
AS5LC2M16
Truth table
CS1
H
X
X
L
L
L
CS2
X
X
L
H
H
H
WE
X
X
X
H
H
H
OE
X
X
X
H
H
L
LB
X
H
X
L
X
L
H
L
L
L
H
L
X
H
L
Key: X = Don’t care, L = Low, H = High.
UB
X
H
X
X
L
H
L
L
H
L
L
Supply
Current
I
SB
I/O0–I/O7 I/O8–I/O15
High Z
High Z
Mode
Standby
I
CC
High Z
D
OUT
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Output disable
I
CC
High Z
D
OUT
D
IN
Read
I
CC
High Z
D
IN
Write
DC Recommended operating condition (over the operating range)
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