May 2001
®
AS4C4M4E1
4M×4 CMOS DRAM (EDO) family
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
- 300 mil, 24/26-pin TSOP
• Low power consumption
- Active: 908 mW max
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
• Refresh
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4E1
- RAS-only or CAS-before-RAS refresh
• 5V power supply
• Latch-up current
≥
200 mA
• ESD protection
≥
2000 volts
• Industrial and commercial temperature available
Pin arrangement
SOJ
V
CC
I/O0
I/O1
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
V
CC
I/O0
I/O1
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
Pin designation
TSOP
24
23
22
21
20
19
18
17
16
15
14
13
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
Pin(s)
A0 to A10
RAS
CAS
WE
I/O0 to I/O3
OE
V
CC
GND
Description
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
Ground
AS4C4M4E0
Selection guide
Symbol
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
5/22/01; v.1.29 point>
AS4C4M4E0
AS4C4M4E1-50
50
25
12
13
85
25
135
2.0
AS4C4M4E1-60
60
30
15
15
100
30
120
2.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
P. 1 of 14
t
RAC
t
CAA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC5
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS4C4M4E1
®
Functional description
The AS4C4M4E1 is a high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as 4,194,304 words × 4
bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low
power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory
in PC, workstation, router and switch applications.
This product features a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active
on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and
prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and CAS going high.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C4M4E1 is a available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The AS4C4M4E1 operates with a
single power supply of 5V ± 0.5V. It provides TTL compatible inputs and outputs.
Logic block diagram for 2K refresh
V
CC
GND
Refresh
controller
Column decoder
Sense amp
Data
I/O
buffers
I/O0 to I/O3
RAS
RAS clock
generator
CAS
CAS clock
generator
WE
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
OE
Address buffers
Row decoder
2048 × 2048 × 4
Array
(16,777,216)
Substrate bias
generator
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
Symbol
V
CC
GND
V
IH
V
IL
Commercial
Industrial
T
A
Min
4.5
0.0
2.4
–0.5
†
0
-40
Nominal
5.0
0.0
–
–
–
–
Max
5.5
0.0
V
CC
0.8
70
85
Unit
V
V
V
V
°C
V
IL
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
5/22/01; v.1.29 point>
Alliance Semiconductor
P. 2 of 14
AS4C4M4E1
®
Absolute maximum ratings
Parameter
Input voltage
Input voltage (DQs)
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
Short circuit output current
Symbol
V
in
V
DQ
V
CC
T
STG
T
SOLDER
P
D
I
out
Min
-1.0
-1.0
-1.0
-55
–
–
–
Max
+7.0
V
CC
+ 0.5
+7.0
+150
260 × 10
1
50
Unit
V
V
V
°C
o
C × sec
W
mA
DC electrical characteristics
-50
Parameter
Input leakage current
Output leakage current
Operating power
supply current
TTL standby power
supply current
Average power supply
current, RAS refresh
mode or CBR
Symbol
I
IL
I
OL
I
CC1
I
CC2
I
CC3
Test conditions
0V
≤
V
in
≤
+5.5V,
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
+5.5V
RAS, CAS Address cycling; t
RC
=min
RAS = CAS
≥
V
IH
RAS cycling, CAS
≥
V
IH
,
t
RC
= min of RAS low after CAS low.
RAS = V
IL
, CAS
address cycling: t
HPC
= min
RAS = CAS = V
CC
- 0.2V
I
OUT
= -5.0 mA
I
OUT
= 4.2 mA
RAS or CAS cycling, t
RC
= min
Min
-5
-5
–
–
Max
+5
+5
135
2.0
Min
-5
-5
–
–
-60
Max
+5
+5
120
2.0
Unit
µA
µA
mA
mA
1,2
Notes
–
120
–
110
mA
1
EDO page mode average
I
CC4
power supply current
CMOS standby power
supply current
Output voltage
CAS before RAS refresh
current
I
CC5
V
OH
V
OL
I
CC6
–
–
2.4
–
–
130
2.0
–
0.4
120
–
–
2.4
–
–
120
2.0
–
0.4
110
mA
mA
V
V
mA
1, 2
5/22/01; v.1.29 point>
Alliance Semiconductor
P. 3 of 14
AS4C4M4E1
®
AC parameters common to all waveforms
-50
Symbol
t
RC
t
RP
t
RAS
t
CAS
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
ASR
t
RAH
t
T
t
REF
t
CP
t
RAL
t
ASC
t
CAH
Parameter
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
CAS precharge time
Column address to RAS lead time
Column address setup time
Column address hold time
Min
80
30
50
8
15
12
10
40
5
0
8
1
–
8
25
0
8
Max
–
–
10K
10K
35
25
–
–
–
–
–
50
32
–
–
–
Min
100
40
60
10
15
12
10
50
5
0
10
1
–
10
30
0
10
-60
Max
–
–
10K
10K
43
30
–
–
–
–
–
50
32
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
4,5
16
6
7
Notes
Read cycle
-50
Symbol
t
RAC
t
CAC
t
AA
t
RCS
t
RCH
t
RRH
Parameter
Access time from RAS
Access time from CAS
Access time from address
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Min
–
–
–
0
0
0
Max
50
12
25
–
–
–
Min
–
–
–
0
0
0
-60
Max
60
15
30
–
–
–
Unit
ns
ns
ns
ns
ns
ns
9
9
Notes
6
6,13
7,13
5/22/01; v.1.29 point>
Alliance Semiconductor
P. 4 of 14
AS4C4M4E1
®
Write cycle
-50
Symbol
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Parameter
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
Data-in hold time
Min
0
10
10
10
8
0
8
Max
–
–
–
–
–
–
–
Min
0
10
10
10
10
0
10
-60
Max
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
12
12
Notes
11
11
Read-modify-write cycle
-50
Symbol
t
RWC
t
RWD
t
CWD
t
AWD
Parameter
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
Min
113
67
32
42
Max
–
–
–
–
Min
135
77
35
47
-60
Max
–
–
–
–
Unit
ns
ns
ns
ns
11
11
11
Notes
Refresh cycle
-50
Symbol
t
CSR
t
CHR
t
RPC
t
CPT
Parameter
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
CAS precharge time
(CBR counter test)
Min
5
8
0
10
Max
–
–
–
Min
5
10
0
10
-60
Max
–
–
–
–
Unit
ns
ns
ns
ns
Notes
3
3
5/22/01; v.1.29 point>
Alliance Semiconductor
P. 5 of 14
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