INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731
Quad 64-bit static shift register
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Quad 64-bit static shift register
FEATURES
•
Frequency range DC to 100 MHz.
•
Separate serial data inputs
•
Cascadable
•
Functionally compatible with
HEF 4731
•
Includes recycling mode
•
Direct shift out
•
Output capability: Standard
•
I
CC
category: LSI.
APPLICATIONS
•
Data storage
•
Delay line.
GENERAL DESCRIPTION
The HC/HCT7731 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no. 7A.
The HC/HCT7731 are quad 64-bit
static shift registers with a recycling
mode. Each register has separate
data inputs D
a
to D
d
, clock inputs CP
a
to CP
d
and data outputs Q
a
to Q
d
.
Data shifts one place towards the
output, each LOW to HIGH transition
of the clock pulse. Each recycling
mode input controls two registers
REC
ab
for registers A and B and
REC
cd
for registers C and D. When
the REC input is HIGH, the device is
in the recycling mode and data at the
output is shifted back into the input of
the register, so after 64 clock pulses
the contents of a register is again in
its original position. This enables the
user to tap off data from any position.
When the REC input is LOW external
data can be shifted in.
C
I
C
PD
Notes
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
74HC/HCT7731
TYP.
SYMBOL
t
PHL
/t
PLH
f
max
PARAMETER
propagation delay
CP
a-d
to Q
a-d
maximum clock
frequency
input capacitance
power dissipation
capacitance per register
notes 1, 2
and 3
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
15
HCT
20
ns
MHz
pF
pF
UNIT
100 100
3.5
58
3.5
61
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= (C
PD
x V
CC2
x f
i
) + (C
L
+ V
CC2
x f
o
) + (I
pull-up
x V
CC
)
where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
V
CC
= supply voltage in V.
C
L
= output load capacitance in pF.
I
pull-up
= pull-up currents in
µA.
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V.
3. See also power dissipation information.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
74HC/HCT7731N
74HC/HCT7731D
PACKAGE
PINS
16
16
PIN POSITION
DIL
SO16
MATERIAL
plastic
plastic
CODE
SOT38Z
SOT109A
September 1993
2
Philips Semiconductors
Product specification
Quad 64-bit static shift register
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: LSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
T
amb
(°C)
SYMBOL
PARAMETER
MIN
t
PHL
/t
PLH
propagation
delay time CP
to Q
n
−
−
−
+25
TYP
50
18
15
19
7
6
19
7
6
8
3
3
22
8
7
−3
−1
−1
−8
−3
−3
26
78
93
MAX
155
31
26
75
15
13
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−40
to
+85
MIN
−
−
−
−
−
−
100
20
17
75
15
13
90
18
15
30
6
5
10
2
2
4.8
24
28
MAX
190
38
32
90
18
15
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−40
to
+125
MIN
−
−
−
−
−
−
120
24
20
90
18
15
110
22
19
35
7
6
15
3
3
4
20
23
MAX
230
46
39
110
22
19
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHZ
MHz
UNIT
74HC/HCT7731
TEST CONDITION
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.4
t
THL
/t
TLH
output transition
−
time
−
−
clock pulse
width
HIGH or LOW
set-up time D
n
to CP
n
set-up time
REC
n
to CP
n
hold time D
n
to
CP
n
hold time REC
n
to CP
n
80
16
14
60
12
10
75
15
13
25
5
4
10
2
2
Fig.4
t
W
Fig.4
t
su
Fig.4
t
su
Fig.5
t
h
Fig.4
t
h
Fig.5
f
max
maximum clock 6
pulse frequency 30
35
Fig.4 (note 1)
Note
1. The maximum power dissipation has to be observed. See power dissipation information.
September 1993
5
FPGA/CPLD
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