INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT75
Quad bistable transparent latch
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad bistable transparent latch
FEATURES
•
Complementary Q and Q outputs
•
V
CC
and GND on the centre pins
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT75
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
1-2
and LE
3-4
). When LE
n-n
is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
n-n
is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LE
n-n
will be stored in the latches. The latched outputs
remain stable as long as the LE
n-n
is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nD to nQ, nQ
LE
n-n
to nQ, nQ
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−1.5
V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
11
3.5
42
12
11
3.5
42
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad bistable transparent latch
PIN DESCRIPTION
PIN NO.
1, 14, 11, 8
2, 3, 6, 7
4
5
12
13
16, 15, 10, 9
SYMBOL
1Q to 4Q
1D to 4D
LE
3-4
V
CC
GND
LE
1-2
1Q to 4Q
NAME AND FUNCTION
complementary latch outputs
data inputs
latch enable input, latches 3 and 4 (active HIGH)
positive supply voltage
ground (0 V)
latch enable input, latches 1 and 2 (active HIGH)
latch outputs
74HC/HCT75
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad bistable transparent latch
FUNCTION TABLE
OPERATING
MODES
data enabled
data latched
Notes
1. H = HIGH voltage level
L = LOW voltage level
q = lower case letters indicate the state of the
referenced output one set-up time prior
to the HIGH-to-LOW LE
n-n
transition
X = don’t care
H
H
L
INPUTS
LE
n-n
L
H
X
nD
OUTPUTS
nQ
L
H
q
H
L
q
nQ
74HC/HCT75
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Quad bistable transparent latch
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to+85
−40
to+125
max.
165
33
28
180
36
31
180
36
31
190
38
32
110
22
19
120
24
20
90
18
15
3
3
3
ns
74HC/HCT75
TEST CONDITIONS
UNIT V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
nD to nQ
propagation delay
nD to nQ
propagation delay
LE
n-n
to nQ
propagation delay
LE
n-n
to nQ
output transition time
33
12
10
39
14
11
33
12
10
39
14
11
19
7
6
80
16
14
60
12
10
3
3
3
17
6
5
14
5
4
−8
−3
−2
110
22
19
120
24
20
120
24
20
125
25
21
75
15
13
100
20
17
75
15
13
3
3
3
140
28
24
150
30
26
150
30
26
155
31
26
95
19
16
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
/ t
PLH
ns
Fig.8
t
PHL
/ t
PLH
ns
Fig.8
t
THL
/ t
TLH
ns
Figs 6 and 7
t
W
enable pulse width
HIGH
set-up time
nD to LE
n-n
hold time
nD to LE
n-n
ns
Fig.8
t
su
ns
Fig.9
t
h
ns
Fig.9
December 1990
5
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