INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7080
16-bit even/odd parity
generator/checker
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
16-bit even/odd parity
generator/checker
FEATURES
•
Word-length easily expanded by cascading
•
Generates either even or odd parity for 16-data bits
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7080 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT7080
The 74HC/HCT7080 are 16-bit parity generators or
checkers commonly used to detect errors in high-speed
data transmission or data retrieval systems.
The even and odd parity output is available for generating
or checking even/odd parity up to 16-bits.
The even/odd parity output (E/O) is HIGH when an even
number of data inputs (I
0
to I
15
) are HIGH and the
cascade/even-odd-changing input (X) is HIGH.
Expansion to larger word sizes is accomplished by
connecting the even/odd parity output (E/O) to the
cascade/even-odd-changing input (X) of the final stage.
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
I
n
to E/O
X to E/O
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
29
12
3.5
24
32
15
3.5
25
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
PIN DESCRIPTION
PIN NO.
1
2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18
10
19
20
SYMBOL
X
I
0
to I
15
GND
E/O
V
CC
74HC/HCT7080
NAME AND FUNCTION
cascade/even-odd-changing input
data inputs
ground (0 V)
even/odd parity output
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
I
n
∑
=E
∑≠
E
Notes
1. H = HIGH voltage level
L = LOW voltage level
E = even
X
H
L
H
L
OUTPUTS
E/O
H
L
L
H
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
I
n
to E/O
propagation delay
X to E/O
output transition time
+25
typ.
91
33
26
41
15
12
19
7
6
−40
to
+85
−40
to
+125
max.
420
84
71
225
45
38
110
22
19
ns
74HC/HCT7080
TEST CONDITIONS
UNIT V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
max. min. max. min.
280
56
48
150
30
26
75
15
13
350
70
60
190
38
33
95
19
16
t
PHL
/ t
PLH
ns
Fig.6
t
THL
/ t
TLH
ns
Figs 6 and 7
December 1990
5
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