Philips Semiconductors
Product specification
Programmable delay timer with oscillator
FEATURES
•
Positive and negative edge
triggered
•
Retriggerable or non-retriggerable
•
Programmable delay
minimum: 100 ns
maximum: depends on input
frequency and division ratio
•
Divide-by range of 2 to 2
24
•
Direct reset terminates output
pulse
•
Very low power consumption in
triggered start mode
•
3 oscillator operating modes:
– RC oscillator
– Crystal oscillator
– External oscillator
•
Device is unaffected by variations
in temperature and V
CC
when using
an external oscillator
•
Automatic power-ON reset
•
Schmitt trigger action on both
trigger inputs
•
Direct drive for a power transistor
•
Low power consumption in active
mode with respect to TTL type
timers
•
High precision due to digital timing
•
Output capability: 20 mA
•
I
CC
category: MSI.
APPLICATIONS
•
Motor control
•
Attic fan timers
•
Delay circuits
•
Automotive applications
•
Precision timing
•
Domestic appliances.
C
I
C
PD
Notes
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
A, B to Q/Q
MR to Q/Q
RS to Q/Q
input capacitance
power dissipation
capacitance per buffer
GENERAL DESCRIPTION
The 74HC/HCT5555 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT5555 are precision
programmable delay timers which
consist of:
•
24-stage binary counter
•
integrated oscillator (using external
timing components)
74HC/HCT5555
•
retriggerable/non-retriggerable
monostable
•
automatic power-ON reset
•
output control logic
•
oscillator control logic
•
overriding asynchronous master
reset (MR).
CONDITIONS
C
L
= 15 pF;
V
CC
= 5 V
24
19
26
TYP.
24
20
28
3.5
36
UNIT
ns
ns
ns
pF
pF
3.5
notes 1 and 2
23
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
x V
CC2
x f
i
+
Σ(C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
Σ(C
L
x V
CC2
x f
o
) = sum of outputs.
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
74HC/HCT5555N
74HC/HCT5555D
PACKAGE
PINS
16
16
PIN POSITION
DIL
SO16
MATERIAL
plastic
plastic
CODE
SOT38Z
SOT109A
September 1993
2
Philips Semiconductors
Product specification
Programmable delay timer with oscillator
74HC/HCT5555
2
handbook, full pagewidth
3
C TC
10
S0
11
S1
12
S2
13
S3
1 RS
OSC
14 CON
R TC
CP
24 - STAGE COUNTER
CD
POWER-ON
RESET
15 MR
4 A
5 B
6 RTR/RTR
MGA644
MONOSTABLE
CIRCUITRY
Q 9
OUTPUT
STAGE
Q 7
Fig.3 Functional diagram.
•
Trigger pulse applied input B for
negative-edge triggering
•
Trigger pulse applied to inputs A
and B (tied together) for both
positive-edge and negative
triggering.
The Schmitt trigger action in the
trigger inputs, transforms slowly
changing input signals into sharply
defined jitter-free output signals and
provides the circuit with excellent
noise immunity.
The OSC CON input is used to select
the oscillator mode, either
continuously running (OSC CON =
HIGH) or triggered start mode (OSC
CON = LOW). The continuously
running mode is selected where a
start-up delay is an undesirable
feature and the triggered start mode
is selected where very low power
consumption is the primary concern.
The start of the programmed time
delay occurs when output Q goes
HIGH (in the triggered start mode, the
previously disabled oscillator will
start-up). After the programmed time
delay, the flip-flop stages are reset
and the output returns to its original
state.
4
FUNCTIONAL DESCRIPTION
The oscillator configuration allows the
design of RC or crystal oscillator
circuits. The device can operate from
an external clock signal applied to the
RS input (R
TC
and C
TC
must not be
connected). The oscillator frequency
is determined by the external timing
components (R
T
and C
T
), within the
frequency range 1 Hz to 4 MHz
(32 kHz to 20 MHz with crystal
oscillator).
In the HCT version the MR input is
TTL compatible but the RS input has
CMOS input switching levels. The RS
input can be driven by TTL input
levels if RS is tied to V
CC
via a pull-up
resistor.
The counter divides the frequency to
obtain a long pulse duration. The
24-stage is digitally programmed via
the select inputs (S
0
to S
3
). Pin S
3
can
also be used to select the test mode,
which is a convenient way of
functionally testing the counter.
The “5555” is triggered on either the
positive-edge, negative-edge or both.
•
Trigger pulse applied to input A for
positive-edge triggering
September 1993
An internal power-on reset is used to
reset all flip-flop stages.
The output pulse can be terminated
by the asynchronous overriding
master reset (MR), this results in all
flip-flop stages being reset. The
output signal is capable of driving a
power transistor. The output time
delay is calculated using the following
formula (minimum time delay is
100 ns):
1
--
×
division ratio (s).
-
f
i
Once triggered, the output width may
be extended by retriggering the
gated, active HIGH-going input A or
the active LOW-going input B. By
repeating this process, the output
pulse period (Q = HIGH, Q = LOW)
can be made as long as desired. This
mode is selected by RTR/RTR =
HIGH. A LOW on RTR/RTR makes,
once triggered, the outputs (Q, Q)
independent of further transitions of
inputs A and B.
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