INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT534
Octal D-type flip-flop; positive
edge-trigger; 3-state; inverting
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Apr 10
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
FEATURES
•
3-state inverting outputs for bus oriented applications
•
8-bit positive, edge-triggered register
•
Common 3-state output enable input
•
Output capability: bus driver
•
I
CC
category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT534
The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “534” is functionally identical to the “374”, but has
inverted outputs.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz.
f
o
= output frequency in MHz.
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
C
L
= output load capacitance in pF.
V
CC
= supply voltage in V.
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
TYPE
NUMBER
74HC534
74HC534
74HCT534
74HCT534
PACKAGE
NAME
SO20
DIP20
SO20
DIP20
DESCRIPTION
plastic small outline package; 20 leads; body width 7.5 mm
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm
plastic dual in-line package; 20 leads (300 mil)
VERSION
SOT163-1
SOT146-1
SOT163-1
SOT146-1
PARAMETER
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
61
3.5
19
HCT
13
40
3.5
19
ns
MHz
pF
pF
UNIT
1998 Apr 10
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
OE
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
SYMBOL
3-state outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
74HC/HCT534
NAME AND FUNCTION
3-state output enable input (active LOW)
fpage
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
MGM954
20 VCC
19 Q7
18 D7
17 D6
page
fpage
1
11
EN
C1
2
5
6
9
12
15
16
19
MGM956
11
CP
3
4
7
8
13
14
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
1D
534
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
17
18
MGM955
18
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Apr 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
handbook, halfpage
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
FF1
to
FF8
3-STATE
OUTPUTS
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
MGM957
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OPERATING MODES
OE
load and read register
load register and disable outputs
L
L
H
H
Note
1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high impedance OFF-state;
↑
= LOW-to-HIGH clock transition.
CP
↑
↑
↑
↑
D
n
l
h
l
h
L
H
L
H
INTERNAL FLIP-FLOPS
Q
0
to Q
7
H
L
Z
Z
OUTPUTS
1998 Apr 10
4
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