INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT533
Octal D-type transparent latch;
3-state; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
FEATURES
•
3-state inverting outputs for bus oriented applications
•
Common 3-state output enable input
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT533 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT533 are octal D-type transparent latches
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
latches.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT533
The “533” consists of eight D-type transparent latches with
3-state inverting outputs. When LE is HIGH, data at the D
n
inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
its corresponding D-input changes.
When LE is LOW the latches store the information that was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the 8 latches are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The “533” is functionally identical to the “373”, “563” and
“573”, but the “373” and “573” have non-inverted outputs
and the “563” and “573” have a different pin arrangement.
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
D
n
to Q
n
LE to Q
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per latch
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
18
3.5
34
16
19
3.5
34
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
OE
Q
0
to Q
7
D
0
to D
7
GND
LE
V
CC
NAME AND FUNCTION
74HC/HCT533
3-state output enable input (active LOW)
3-state latch outputs
data inputs
ground (0 V)
latch enable input (active HIGH)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
FUNCTION TABLE
INPUTS
OPERATING
MODES
OE LE D
n
enable and
read register
(transparent
mode)
latch and
read register
latch register
and disable
outputs
Fig.4 Functional diagram.
Notes
L
L
H
H
L
H
74HC/HCT533
INTERNAL OUTPUTS
LATCHES Q TO Q
0
7
L
H
H
L
L
L
H
H
L
L
X
X
l
h
X
X
L
H
X
X
H
L
Z
Z
1. H = HIGH voltage level
h = HIGH voltage level one set-up prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up prior to the
HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
Fig.5 Logic diagram (one latch).
Fig.6 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state;
inverting
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
propagation delay
LE to Q
n
3-state output enable
time
OE to Q
n
3-state output disable
time
OE to Q
n
output transition time
+25
typ.
47
17
14
58
21
17
44
16
13
50
18
14
14
5
4
80
16
14
50
10
9
35
7
6
14
5
4
3
1
1
3
1
1
−40
to
+85
max. min.
150
30
26
175
35
30
150
30
26
150
30
26
60
12
10
100
20
17
65
13
11
45
9
8
max.
190
38
33
220
44
37
190
38
33
190
38
33
75
15
13
120
24
20
75
15
13
55
11
9
−40
to
+125
min.
max.
225
45
38
265
53
45
225
45
38
225
45
38
90
18
15
ns
74HC/HCT533
TEST CONDITIONS
UNIT V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
ns
Fig.8
t
PZH
/ t
PZL
ns
Fig.9
t
PHZ
/ t
PLZ
ns
Fig.9
t
THL
/ t
TLH
ns
Fig.7
t
W
LE pulse width
HIGH
set-up time
D
n
to LE
hold time
D
n
to LE
ns
Fig.8
t
su
ns
Fig.10
t
h
ns
Fig.10
December 1990
5
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