INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4538
Dual retriggerable precision
monostable multivibrator
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Dual retriggerable precision monostable
multivibrator
FEATURES
•
Separate reset inputs
•
Triggering from leading or trailing edge
•
Output capability: standard
•
I
CC
category: MSI
•
Power-on reset on-chip
GENERAL DESCRIPTION
The 74HC/HCT4538 are high-speed Si-gate CMOS
devices and are pin compatible with “4538” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4538 are dual retriggerable-resettable
monostable multivibrators. Each multivibrator has an
active LOW trigger/retrigger input (nA
0
), an active HIGH
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4538
trigger/retrigger input (nA
1
) , an overriding active LOW
direct reset input (nR
D
), an output (nQ) and its complement
(nQ), and two pins (nC
TC
and nRC
TC
) for connecting the
external timing components C
t
and R
t
. Typical pulse width
variation over temperature range is
±
0.2%.
The “4538” may be triggered by either the positive or the
negative edges of the input pulse. The duration and
accuracy of the output pulse are determined by the
external timing components C
t
and R
t
. The output pulse
width (T) is equal to 0.7
×
R
t
×
C
t
. The linear design
techniques guarantee precise control of the output pulse
width.
A LOW level at nR
D
terminates the output pulse
immediately.
Schmitt-trigger action in the trigger inputs makes the circuit
highly tolerant to slower rise and fall times.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
)
+
+
0.48
×
C
EXT
×
V
CC2
×
f
o
+
D
×
0.8
×
V
CC
where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
D = duty factor in %
C
EXT
= timing capacitance in pF
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA
0
, nA
1
to nQ, nQ
input capacitance
power dissipation capacitance per multivibrator notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
27
3.5
136
HCT
30
3.5
138
ns
pF
pF
UNIT
September 1993
2
Philips Semiconductors
Product specification
Dual retriggerable precision monostable
multivibrator
PIN DESCRIPTION
PIN NO.
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
SYMBOL
1C
TC
, 2C
TC
1RC
TC
, 2RC
TC
1R
D
, 2R
D
1A
1
, 2A
1
1A
0
, 2A
0
1Q, 2Q
1Q, 2Q
GND
V
CC
NAME AND FUNCTION
external capacitor connections
external resistor/capacitor connections
direct reset inputs (active LOW)
trigger inputs (LOW-to-HIGH, edge-triggered)
trigger inputs (HIGH-to-LOW, edge-triggered)
pulse outputs
complementary pulse outputs
ground (0 V)
positive supply voltage
74HC/HCT4538
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Dual retriggerable precision monostable
multivibrator
FUNCTION TABLE
INPUTS
nA
0
↓
H
X
Notes
1. H
L
X
↑
↓
nA
1
L
↑
X
nR
D
H
H
L
74HC/HCT4538
OUTPUTS
nQ
nQ
L
H
Fig.4 Functional diagram.
= HIGH voltage level
= LOW voltage level
= don’t care
= LOW-to-HIGH transition
= HIGH-to-LOW transition
= one HIGH level output pulse
= one LOW level output pulse
(1) Connect C
TC
(pins 1 and 15) to GND (pin 8).
Fig.5
Connection of the external timing
components R
t
and C
t
.
(1) Positive edge triggering.
(2) Positive edge retriggering (pulse
lengthening).
(3) Negative edge triggering.
(4) Reset (pulse shortening).
(5) V
ref1
and V
ref2
are internal reference voltages.
(6) T = 0.7
×
R
t
×
C
t
(see also Fig.5).
Fig.6 Timing diagram.
September 1993
4
FPGA/CPLD
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