INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4516
Binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Binary up/down counter
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4516 are high-speed Si-gate CMOS
devices and are pin compatible with the “4516” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4516 are edge-triggered synchronous
up/down 4-bit binary counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
Logic equation for terminal count:
TC = CE . {(UP/DN) . Q
0
. Q
1
. Q
2
. Q
3
+ (UP
⁄
DN ) . Q
0
. Q
1
. Q
2
. Q
3
}
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4516
parallel load input (PL), four parallel inputs (D
0
to D
3
), four
parallel outputs (Q
0
to Q
3
), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D
0
to D
3
is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. When PL and CE are
LOW, the counter changes on the LOW-to-HIGH transition
of CP. UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up, TC is LOW when Q
0
to Q
3
are HIGH and CE is LOW.
When counting down, TC is LOW when Q
0
to Q
3
and CE
are LOW. A HIGH on MR resets the counter (Q
0
to
Q
3
= LOW) independent of all other input conditions.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
PARAMETER
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
19
45
3.5
59
HCT
19
57
3.5
61
ns
MHz
pF
pF
UNIT
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Binary up/down counter
PIN DESCRIPTION
PIN NO.
1
4, 12, 13, 3
5
6, 11, 14, 2
7
8
9
10
15
16
SYMBOL
PL
D
0
to D
3
CE
Q
0
to Q
3
TC
GND
MR
UP/DN
CP
V
CC
NAME AND FUNCTION
parallel load input (active HIGH)
parallel inputs
count enable input (active LOW)
parallel outputs
terminal count output (active LOW)
ground (0 V)
74HC/HCT4516
asynchronous master reset input (active HIGH)
up/down control input
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
December 1990
3
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