M67201A/M67202A
512
9 & 1 K
9 CMOS Parallel FIFO
Introduction
The M67201A/202A implement a first-in first-out
algorithm, featuring asynchronous read/write operations.
The FULL and EMPTY flags prevent data overflow and
underflow. The Expansion logic allows unlimited
expansion in word size and depth with no timing
penalties. Twin address pointers automatically generate
internal read and write addresses, and no external address
information are required for the TEMIC FIFOs. Address
pointers are automatically incremented with the write pin
and read pin. The 9 bits wide data are used in data
communications applications where a parity bit for error
checking is necessary. The Retransmit pin reset the Read
pointer to zero without affecting the write pointer. This is
very useful for retransmitting data when an error is
detected in the system.
Using an array of eigh transistors (8 T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the M 67201A/202A combine an
extremely low standby supply current (typ = 1.0
µA)
with
a fast access time at 25 ns over the full temperature range.
All versions offer battery backup data retention capability
with a typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels
of
performance
and
reliability
the
M 67201A/202A is processed according to the methods
of the latest revision of the MIL STD 883 (class B or S)
and/or ESA SCC 9000.
Features
D
D
D
D
First-in first-out dual port memory
512
×
9 organisation (M 67201A)
1024
×
9 organisation (M 67202A)
Fast access time
20*, 25, 35, 45, 55 ns, commercial, industrial and
automotive
20*, 25, 30, 40, 50 ns, military
D
Wide temperature range :
– 55°C to + 125°C
D
67201AL/202AL low power 67201AV/202AV very low
power
D
Fully expandable by word width or depth
* Preview. Please Consult Sales.
D
D
D
D
D
D
D
D
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V
±
10 % Power Supply (1)
High performance SCMOS technology
(1) 3.3 V versions are also available. Please consult sales.
MATRA MHS
Rev. D (11 April. 97)
1
M67201A/M67202A
Interface
Block Diagram
Pin Configuration
SO plastic 28 pin 300 mils(*)
DIL plastic 28 pin 300 mils
DIL ceramic 28 pin 300 mils
FP 28 pin 400 mils (Preview)
SO/DIL (top view)
INDEX
32 pin LCC and PLCC
LCC (top view)
W
NC
V
CC
I
4
I
3
I
8
I
5
(*) On request only.
2
GND
NC
R
Q
4
Q
5
Q
3
Q
8
W
I
8
I
3
I
2
I
1
I
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
4
I
5
I
6
I
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
I
2
I
1
I
0
XI
FF
Q
0
Q
1
NC
Q
2
4 3 2
32 31 30
1
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14 15 16 17 18 19 20
I
6
I
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Pin Names
NAMES
I0–8
Q0–8
W
R
RS
EF
Inputs
Outputs
Write Enable
Read Enable
Reset
Empty Flag
DESCRIPTION
NAMES
FF
XO/HF
XI
FL/RT
VCC
GND
DESCRIPTION
Full Flag
Expansion Out/Half–Full Flag
Expansion IN
First Load/Retransmit
Power Supply
Ground
Signal Description
Data In (I0 - I8)
Data inputs for 9 - bit data
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
the Read Enable (R) and Write Enable (W) inputs must be
in the high state during the period shown in figure 1 (i.e.
t
RSS
before the rising edge of RS) and should not change
until t
RSR
after the rising edge of RS. The Half-Full flag
(HF will be reset to high after Reset (RS).
RESET (RS)
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
Figure 1. Reset.
Notes :
1. EF, FF and HF may change status during reset, but flags will be valid at t
RSC
.
2. W and R = VIH around the rising edge of RS.
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
Once half of the memory is filled, and during the falling
edge of the next write operation, the Half-Full Flag (HF)
will be set to low and remain in this state until the
difference between the write and read pointers is less than
MATRA MHS
Rev. D (11 April. 97)
or equal to half of the total available memory in the
device. The Half-Full Flag (HF) is then reset by the rising
edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
stack is full, the internal write pointer is blocked from W,
so that external changes to W will have no effect on the
full FIFO stack.
3
M67201A/M67202A
Read Enable (R)
A read cycle is initiated on the falling edge of the Read
Enable (R) provided that the Empty Flag (EF) is not set.
The data is accessed on a first in/first out basis, not with
standing any current write operations. After Read Enable
(R) goes high, the Data Outputs (Q0 - Q8) will return to
a high impedance state until the next Read operation.
When all the data in the FIFO stack has been read, the
Empty Flag (EF) will go low, allowing the “final” read
cycle, but inhibiting further read operations whilst the
data outputs remain in a high impedance state. Once a
valid write operation has been completed, the Empty Flag
(EF) will go high after tWEF and a valid read may then
be initiated. When the FIFO stack is empty, the internal
read pointer is blocked from R, so that external changes
to R will have no effect on the empty FIFO stack.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write
operations when the write pointer is one location less than
the read pointer, indicating that the device is full. If the
read pointer is not moved after Reset (RS), the Full Flag
(FF) will go low after 512/1024 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read
operations when the read pointer is equal to the write
pointer, indicating that the device is empty.
Expansion Out/Half-full Flag (XO/HF)
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is connected to ground, this
output acts as an indication of a half-full memory.
After half the memory is filled and on the falling edge of
the next write operation, the Half-Full Flag (HF) will be
set to low and will remain set until the difference between
the write and read pointers is less than or equal to half of
the total memory of the device. The Half-Full Flag (HF)
is then reset by the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is
connected to Expansion Out (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last memory location.
First Load/Retransmit (FL/RT)
This is a dual-purpose input. In the Depth Expansion
Mode, this pin is connected to ground to indicate that it
is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The
Single Device Mode is initiated by connecting the
Expansion In (XI) to ground.
The M 67201A/202A can be made to retransmit data
when the Retransmit Enable Control (RT) input is pulsed
low. A retransmit operation will set the internal read point
to the first location and will not affect the write pointer.
Read Enable (R) and Write Enable (W) must be in the
high state during retransmit. The retransmit feature is
intended for use when a number of writes equals to or less
than the depth of the FIFO have occured since the last RS
cycle. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag
(HF), in accordance with the relative locations of the read
and write pointers.
Data Output (Q
0
- Q
8
)
DATA output for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is
connected to GND to indicate an operation in the single
device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain modes.
4
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Functional Description
Operating Modes
Single Device Mode
A single M 67201A/202A may be used when the
application requirements are for 512/1024 words or less.
Figure 2. Block Diagram of Single 512
×
9 and 1024
×
9.
HF
(HALF–FULL FLAG)
WRITE
(W)
9
DATA
IN
(I)
(R)
9
READ
The M 67201A/202A is in a Single Device Configuration
when the Expansion In (XI) control input is grounded (see
Figure 2). In this mode the Half-Full Flag (HF), which is
an active low output, is shared with Expansion Out (XO).
M
67201A
67202A
Q
DATA
OUT
FULL FLAG (FF)
RESET
(RS)
(EF) EMPTY FLAG
(RT) RETRANSMIT
EXPANSION IN (XI)
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices.
Status flags (EF, FF and HF) can be detected from any
device. Figure 3 demonstrates an 18-bit word width by
using two M 67201A/202A. Any word width can be
attained by adding additional M 67201A/202A.
Figure 3. Block Diagram of 512 / 1024
×
18 FIFO Memory Used in Width Expansion Mode.
HF
9
DATA
IN
(1)
(R) READ
WRITE
FULL FLAG
RESET
(RS)
9
9
XI
XI
18
(Q)DATA
OUT
Note :
3. Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width
expansion configuration. Do not connect any output control signals together.
(W)
(FF)
HF
9
18
M
67201A/202A
M
67201A/202A
(EF) EMPTY FLAG
(RT) RETRANSMIT
MATRA MHS
Rev. D (11 April. 97)
5
NXP MCU
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