INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC4049
Hex inverting high-to-low level
shifter
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Hex inverting high-to-low level shifter
FEATURES
•
Output capability: standard
•
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC4049 is a high-speed Si-gate CMOS device and
is pin compatible with the “4049” of the “4000B” series. It
is specified in compliance with JEDEC standard no. 7A.
The 74HC4049 provides six inverting buffers with a
modified input protection structure, which has no diode
connected to V
CC
. Input voltages of up to 15 V may
therefore be used.
74HC4049
This feature enables the inverting buffers to be used as
logic level translators, which will convert high level logic to
low level logic, while operating from a low voltage power
supply. For example 15 V logic (“4000B series”) can be
converted down to 2 V logic.
The actual input switch level remains related to the V
CC
and is the same as mentioned in the family characteristics.
At the same time each part can be used as a simple
inverter without level translation.
APPLICATIONS
•
Converting 15 V logic (“4000B” series) down to 2 V logic.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer note 1
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
8
3.5
14
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Hex inverting high-to-low level shifter
74HC4049
Fig.5
Fig.4 Functional diagram.
Input protection for HC4049. Single sided thick
oxide field effect metal gate transistor as input
protection.
Fig.6 Logic diagram (one level shifter).
FUNCTION TABLE
INPUT
nA
L
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
OUTPUT
nY
H
L
December 1990
4
Philips Semiconductors
Product specification
Hex inverting high-to-low level shifter
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
V
CC
V
IK
−I
IK
±I
OK
±I
O
±I
CC
;
±I
GND
T
stg
PARAMETER
DC supply voltage
DC input voltage range
DC input diode current
DC output diode current
DC output source or sink current
- standard outputs
DC V
CC
or GND current for types
with:
- standard outputs
storage temperature range
power dissipation per package
P
tot
plastic DIL
plastic mini-pack (SO)
RECOMMENDED OPERATING CONDITIONS
74HC
SYMBOL
V
CC
V
I
T
amb
T
amb
PARAMETER
min.
DC supply voltage
DC input voltage range
2.0
GND
−
typ.
5.0
max.
6.0
15
+85
+125
1000
500
400
650
1000
V
V
°C
°C
UNIT
750
400
mW
mW
−65
MIN.
−0.5
−0.5
MAX.
+7
+16
20
20
25
UNIT
V
V
mA
mA
mA
for V
I
< −0.5
V
74HC4049
CONDITIONS
for V
O
< −0.5
V or V
O
>
V
CC
+0.5 V
for
−0.5
V
<
V
O
<
V
CC
+0.5 V
50
+150
mA
°C
for temperature range:
−40
to +125
°C
74HC
above +70
°C:
derate linearly with 12 mW/K
above +70
°C:
derate linearly with 8 mW/K
CONDITIONS
operating ambient temperature range
−40
operating ambient temperature range
−40
see DC and AC
characteristics
V
CC
= 2.0 V; V
IN
= 2.0 V
V
CC
= 4.5 V; V
IN
= 4.5 V
V
CC
= 6.0 V; V
IN
= 6.0 V
V
CC
= 6.0 V; V
IN
= 10.0 V
V
CC
= 6.0 V; V
IN
= 15.0 V
t
r
, t
f
input rise and fall times
6.0
ns
December 1990
5
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