SL74LV373
OCTAL D-TYPE TRANSPARENT LATCH
(3-State)
SL74LV373 are compatible by pinning with SL74HC373 and
SL74HCT373 series. Input voltage levels are compatible with
standard CMOS levels.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Voltage supply range: 2.0 to 3.2 V
•
LOW input current: 1.0
µÀ;
0.1
µÀ
at Ò = 25
°Ñ
•
Input current LOW/HIGH: 8 mÀ
•
Latch current: not less than 150 mÀ at Ò = 125
°Ñ
•
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
•
BLOCK DIAGRAM
ORDERING INFORMATION
SL74LV373N Plastic DIP
SL74LV373D SOIC
T
A
= -40° to 125° C
for all packages
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
03
04
07
08
13
14
17
18
02
05
06
09
12
15
16
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
OE
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
PIN ASSIGNMENT
01
02
03
04
05
20
19
18
17
16
V
CC
Q
7
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
LE
373
06
07
08
09
10
15
14
13
12
11
19
Q
7
11
GND
LE
OE
01
Pin 20=V
CC
Pin 10 = GND
OE
L
L
L
H
FUNCTION TABLE
Inputs
LE
H
H
L
X
Dn
H
L
X
X
Output
Qn
H
L
no change
Z
SLS
System Logic
Semiconductor
SL74LV373
ABSOLUTE MAXIMUM RATINGS*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
Supply voltage
Input diode current
Output diode current
Output source or sink current
V
CC
current
GND current
Power dissipation per package:
Plastic DIP *
4
SOIC *
4
Storage temperature range
Parameter
Rating
-0.5 to +5.0
±20
±50
±35
±70
±70
750
500
-65 to +150
°C
Unit
V
mÀ
mÀ
mÀ
mÀ
mÀ
mW
Tstg
*
In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute
maximum ratings functioning is guarateed at the recommended operatng conditions.
*
1
Provided V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
Provided V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
Provided -0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
When operating in the temperature range of 70°Ñ to 125°C power dissipation value decreses:
- for Plastic DIP by 12 mW/°C
- for SOIC by
8
mW/°C
RECOMMENDED OPERAING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
LH
, t
HL
Supply voltage
Input voltage
Output voltage
Operating ambient temperature range.
For all types of packages
Input rise and fall times
V
CC
=1.2 V
V
CC
=2.0 V
V
CC
=3.0 V
V
CC
=3.6 V
Parameter
Min
1.2
0
0
-40
0
Max
3.6
V
CC
V
CC
125
1000
700
500
400
Unit
V
V
V
°C
ns
SLS
System Logic
Semiconductor
SL74LV373
DC CHARACTERISTICS
Test
Symbol
Parameter
conditions
V
CC
,
V
25°C
min max
V
IH
HIGH level
voltage
V
O
= V
CC
-0.1 V
1.2
2.0
3.0
3.6
1.2
2.0
3.0
3.6
1.2
2.0
3.0
3.6
3.0
1.2
2.0
3.0
3.6
3.0
3.6
3.6
0.9
1.4
2.1
2.5
-
-
-
-
1.1
1.92
2.92
3.52
2.48
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.09
0.09
0.09
0.09
0.33
±0.1
±0.5
Limits
-40°C to 85°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.34
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.4
±1.0
±5
125°C
min
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
2.20
-
-
-
-
-
-
-
max
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
-
0.1
0.1
0.1
0.1
0.5
±1.0
±10
V
Unit
V
IL
LOW level
voltage
V
O
=0.1 V
V
V
OH
HIGH level
output voltage
V
I
= V
IH
or V
IL
I
O
= -50
µÀ
V
V
I
= V
IH
or V
IL
I
O
= -8 mÀ
V
OL
LOW level
output voltage
V
I
= V
IH
or V
IL
I
O
= 50
µÀ
V
V
V
I
= V
IH
or V
IL
I
O
= 8 mÀ
I
I
I
OZ
Input current
OFF-state
output current
V
I
= V
CC
or 0 V
3-state outputs
V
I
= V
IL
or V
IH
V
O
=V
CC
or
0V
V
I
=V
CC
or 0 V
I
O
= 0
µÀ
V
µÀ
µÀ
I
CC
Supply current
3.6
-
8.0
-
80
-
160
µÀ
SLS
System Logic
Semiconductor
SL74LV373
AC CHARACTERISTICS
(C
L
=50 pF, t
LH
= t
HL
= 6.0 ns)
Test
Symbol
Parameter
conditions
V
CC
,
V
25°C
Limits
-40°C to 85°C
max
190
48
29
230
56
34
200
43
28
200
50
30
100
20
13
-
-
-
-
-
-
-
-
-
-
-
125°C
min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
450
41
24
100
15
12
25
5
5
-
-
max
220
58
35
270
68
41
240
45
32
240
60
36
120
24
15
-
-
-
-
-
-
-
-
-
-
-
pF
ns
Unit
min max min
t
PHL,
t
PLH
Propagation delay Figure 1
from Dn to Qn
t
PHL,
t
PLH
Propagation delay Figure 2
from LE to Qn
t
PHZ
t
PLZ
3-state output
from OE to Qn enable time
t
PZH
t
PZL
3-state disable
from OE to Qn time
t
THL,
t
TLH
Figure 4
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
3.0
V
I
= 0 V or
V
CC
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
250
30
18
45
15
9
25
5
5
-
-
150
38
23
180
45
27
160
35
23
160
40
24
75
16
10
-
-
-
-
-
-
-
-
-
7
80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
350
34
20
50
17
10
25
5
5
-
-
Figure 4
HIGH-to-LOW and Figures 1,2
LOW-to-HIGH
transition time
Clock pulse width
HIGH or LOW
Set-up time Dn to
LE
Hold time Dn to
LE
Input capacitance
Power dissipation
capacitance (per
flip-flop)
Figure 2
t
W
t
SU
Figure 3
t
H
Figure 3
C
I
C
PD
SLS
System Logic
Semiconductor
SL74LV373
t
LH
0.9
Dn
V
1
0.1
t
PLH
V
1
t
HL
0.9
V
CC
0.1
t
PHL
GND
0.9
V
1
0.1
t
TLH
V
1
= 0.5V
CC
0.9
V
1
0.1
0
V
B
Qn
t
THL
Figure 1 - Time diagram
t
LH
0.9
LE
0.1
V
1
t
W
t
PLH
t
PHL
V
1
V
1
GND
V
CC
0.9
V
1
Qn
0.1
t
TLH
V
1
= 0.5V
CC
0.9
V
1
0.1
0
V
B
t
THL
Figure 2 - Time diagram
.
SLS
System Logic
Semiconductor
嵌入式系统
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