2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins
their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3 AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power
supply pins.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 15
June 2005
rev 0.3
‘SpreadTrak’
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5I9772A is designed so as not to filter off the Spread
Spectrum feature of the Reference Input, assuming it
exists.
ASM5I9772A
When a zero delay buffer is not designed to pass the
Spread Spectrum feature through, the result is a
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Table 1. Frequency Table
Feedback Output
Divider
÷4
÷6
÷8
÷10
÷12
÷16
÷20
÷24
÷32
÷40
VCO
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 10
Input Clock * 12
Input Clock * 16
Input Clock * 20
Input Clock * 24
Input Clock * 32
Input Clock * 40
Input Frequency Range
(AVDD = 3.3V)
50 MHz to 125 MHz
33.3 MHz to 83.3 MHz
25 MHz to 62.5 MHz
20 MHz to 50 MHz
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
10 MHz to 25 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
5 MHz to 12.5 MHz
Input Frequency Range
(AVDD =2.5V)
50 MHz to 95 MHz
33.3 MHz to 63.3 MHz
25 MHz to 47.5 MHz
20 MHz to 38 MHz
16.6 MHz to 31.6 MHz
12.5 MHz to 23.75 MHz
10 MHz to 19 MHz
8.3 MHz to 15.8 MHz
6.25 MHz to 11.8 MHz
5 MHz to 9.5MHz
Table 2. Function Table (Configuration Controls)
Control
REF_SEL
TCLK_SEL
VCO_SEL
PLL_EN
INV_CLK
Default
1
1
1
1
1
TCLK0, TCLK1
TCLK0
0
Crystal oscillator
TCLK1
1
VCO÷2 (low input frequency range)
Bypass mode, PLL disabled. The input clock
connects to the output dividers
QC2 and QC3 are in phase with QC0 and QC1
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the VCO running at its minimum
frequency. The device is reset by the internal
power-on reset (POR) circuitry during power-up.
VCO÷1 (high input frequency range)
PLL enabled. The VCO output
connects to the output dividers
QC2 and QC3 are inverted (180°
phase shift) with respect to QC0 and
QC1
MR#/OE
1
Outputs enabled
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 15
June 2005
rev 0.3
Table 3. Function Table (Bank A)
VCO_SEL
0
0
0
0
1
1
1
1
ASM5I9772A
Table 5. Function Table (Bank C)
QA(0:3)
÷8
÷12
÷16
÷24
÷4
÷6
÷8
÷12
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
VCO_SEL
0
0
0
0
1
1
1
1
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC(0:3)
÷4
÷8
÷12
³16
÷2
÷4
÷6
÷8
Table 4. Function Table (Bank B)
VCO_SEL
0
0
0
0
1
1
1
1
Table 6. Function Table (FB_OUT)
QB(0:3)
÷8
÷12
÷16
÷20
÷4
÷6
÷8
÷10
SELB1
0
0
1
1
0
0
1
1
SELB0
0
1
0
1
0
1
0
1
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷12
÷16
÷20
÷16
÷24
÷32
÷40
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Absolute Maximum Conditions
Parameter
VDD
VDD
V
IN
V
OUT
V
TT
LU
R
PS
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
H
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch-up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to VSS
Relative to VSS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Manufacturing test
Min
-0.3
2.375
-0.3
-0.3
-
200
-
-65
-40
-
-
-
2000
10
Max
5.5
3.465
VDD+ 0.3
VDD+ 0.3
VDD ÷2
-
150
+150
+85
+150
23
55
-
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
V
ppm
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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