INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT273
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FEATURES
•
Ideal buffer for MOS microprocessor or memory
•
Common clock and master reset
•
Eight positive edge-triggered D-type flip-flops
•
See “377” for clock enable version
•
See “373” for transparent latch version
•
See “374” for 3-state version
•
Output capability; standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT273
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
CP to Q
n
MR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
15
66
3.5
20
15
20
36
3.5
23
ns
ns
MHz
pF
pF
HCT
UNIT
September 1993
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
MR
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
NAME AND FUNCTION
master reset input (active LOW)
flip-flop outputs
data inputs
ground (0 V)
74HC/HCT273
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FUNCTION TABLE
OPERATING
MODES
reset (clear)
load “1”
load “0”
Note
74HC/HCT273
INPUTS
MR
L
H
H
CP
X
↑
↑
D
n
X
h
I
OUTPUTS
Q
n
L
H
L
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
↑
= LOW-to-HIGH transition
X = don’t care
Fig.4 Functional diagram.
Fig.5 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
propagation delay
MR to Q
n
output transition time
+25
typ.
41
15
13
44
16
14
19
7
6
80
16
14
14
5
4
17
6
5
−6
−2
−2
11
4
3
−6
−2
−2
20.6
103
122
max.
150
30
26
150
30
26
75
15
13
100
20
17
75
15
13
65
13
11
75
15
13
3
3
3
4.8
24
28
−40
to
+85
min.
max.
185
37
31
185
37
31
95
19
15
120
24
20
90
18
15
75
15
13
90
18
15
3
3
3
4.0
20
24
−40
to
+125
min.
max.
225
45
38
225
45
38
110
22
19
ns
74HC/HCT273
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
ns
Fig.6
t
W
master reset pulse width 60
LOW
12
10
removal time
MR to CP
set-up time
D
n
to CP
hold time
D
n
to CP
maximum clock pulse
frequency
50
10
9
60
12
10
3
3
3
6.0
30
35
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.8
t
h
ns
Fig.8
f
max
MHz
Fig.6
September 1993
5
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