Standard Products
CT2512-PCB/2513-PCB/2511-PCB/2511-PCB
Dual Redundant Remote Terminal
for MIL-STD-1553B in PCB Style
www.aeroflex.com/Avionics
September 21, 2005
FEATURES
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CT2512-PCB Replaces DDC BUS-65112 and BUS-65117
CT2513-PCB Replaces DDC BUS-65113 and BUS-65118
CT2510-PCB Replaces DDC BUS-65110 and BUS-65120
CT2511-PCB Replaces DDC BUS-65111 and BUS-65121
Functions as a Complete Remote Terminal Unit
Supports 13 Mode Codes, Illegalization of Codes Allowed
Transfers Data with DMA Type Handshaking
Latched Outputs for Command Word and Word Count
14 Bit Built-ln-Test Word Register
4 Error Flag Outputs
Advanced Low Power VLSI Technology
COTs PCB Construction
Designed for Commercial, Industrial and Aerospace Applications
GENERAL DESCRIPTION
Aeroflex’s CT2512-PCB contains 2 transceivers, 2 encoder/decoders, bit processors and complete Remote Terminal
(RT) logic. The device is constructed using Aeroflex advanced VLSI custom chip and hybrid technology. It functions
as a complete dual redundant MIL-STD-1553B RT Unit supporting all 13 mode codes for dual redundant operation.
The CT2512-PCB is a pin-for-pin functional equivalent of the DDC BUS-65112/117 and performs parallel data
transfers with a DMA type handshake. Multiple error flag outputs and host access to many of the RT Status Word bits
are just some of the features that make this part ideal for many RT applications. The unit has an operating range of
-55°C to +125°C.
See "Ordering Information" (last sheet) for CT2513-PCB / CT2510-PCB / CT2511-PCB.
DATA BUS A
DUAL
TRANSCEIVER
DATA BUS B
ENCODER/
DECODER
MIL-STD-1553B
PROTOCOL
AND
BIT
I/O
INTERFACE
DB0-DB15
A0-A11
ERROR FLAG
TIMING FLAGS
STATUS BITS
ENCODER/
DECODER
PROCESSING
LOGIC
FIGURE 1 – FUNCTIONAL BLOCK DIAGRAM
SCDCT2512PCB Rev A
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage (V
CC
)
(Pins 18, 76)
Power Supply Voltage (V
EE
)
(Pins 38, 57)
Power Supply Voltage (V
CCL
)
(Pins 37, 58 / 51)
Receiver Differential Input
(Pins 20, 59 / 74, 36)
Receiver Input Voltage
(Pins 20, 59 / 74, 36)
Driver Output Current
(Pins 56, 17 / 39, 77)
Transmission Duty Cycle at T
PCB
= 100°C
Operating Temperature Range
Note: 1/ T
PCB
is PCB Bottom surface temperature under Transceiver.
1/
Limits
-0.3 to +18.0
+0.3 to -18.0
-0.3 to +7.0
±20 (40Vp-p)
±15
+200
100
-55 to +125
Units
Volts
Volts
Volts
Volts
Volts
mA
%
°C
POWER AND THERMAL DATA (SINGLE TRANSCEIVER AND LOGIC SECTION)
Parameter/Conditions
Power Supply Voltage
Symbol
V
CC
V
EE
V
CCL
4/
Min
14.25
-14.25
4.5
-
-
-
-
-
-
-
Typ
15
-15
5
10
2
0
12
20
90
180
Max
15.75
-15.75
5.5
-
-
5
20
50
100
200
Units
V
V
V
°C/W
W
mA
mA
mA
mA
mA
Thermal Resistance, most critical device
Ø
JC
P
C
I
CC
I
EE
2/
I
CCL
2/
I
CC
@ 25%
I
CC
@ 100%
Power dissipation of most critical (hottest) device during
1/
continuous transmission (100% duty cycle)
Total supply current standby mode, or transmitting at less
than 1% duty cycle (e.g. 20us of transmission every 2ms or
longer interval)
Total supply current transmitting at 1Mhz into a 35-ohm
load at point A in Figure 2
3/
Notes
1/ Decreases linearly to zero at zero duty cycle.
2/ Limit does not change with mode of operation or duty cycle.
3/ Decreases linearly to applicable "standby" values at zero duty cycle.
4/ Referenced to T
PCB
ELECTRICAL CHARACTERISTICS (RECEIVER SECTION)
Parameter/Conditions
Differential input impedance DC to 1MHz
Point A
Point B
Differential voltage range
Input common mode voltage range
Common mode rejection ratio (from Point A, Figure 1)
Threshold characteristics, Sine wave at 1MHz
Note: Threshold voltages refer to Point A or Point B - Figure 2.
Point A
Point B
SCDCT2512PCB Rev A
Symbol
Z
IN
V
DIR
V
ICR
CMMR
Min
2K
1K
±20V
±10V
40
Max
-
-
-
-
-
Units
Ω
Ω
Vpeak
Vpeak
dB
V
TH
0.6
0.4
1.2
0.86
Vp-p
Vp-p
2
ELECTRICAL CHARACTERISTICS (TRANSMITTER SECTION)
Parameter/Conditions
Differential output level, Figure 1 (145 Ohm load)
Point A
Point B
Rise and Fall times
(10% to 90% of p-p output) Point A or Point B
Output offset, Figure 2 (35-ohm load)
2.5us after mid-bit crossing of parity bit of last word of a 660us
message
Point A
Point B
Differential output noise
Point A
Point B
Symbol
V
O
T
r
Min
6
18
100
Typ
7.5
20
-
Max
9
27
300
Units
Vp-p
Vp-p
nS
V
OS
-90
-250
-
-
-
-
-
-
+90
+250
5
14
mVpeak
mVpeak
mVp-p
mVp-p
V
NOI
LOGIC CHARACTERISTICS
Symbol
V
IH
V
IL
I
IL
I
IH
I
IL
I
IH
V
OH
V
OL
Note 1:
Parameter
Input "1"
Input "0"
Input l
Input l
Input l
Input l
Output "1"
Output "0"
Min
2.4
-
-650
-650
-20
-20
2.7
-
Typ
-
-
-
-
-
-
-
-
Max
-
0.7
-100
-100
+20
+20
-
0.4
Units
V
DC
V
DC
µA
µA
µA
µA
V
DC
V
DC
Conditions
Note 1A
Note 1B
Note 2A
Note 1B
Note 3A/4A
Note 3B/4B
For INPUT pins 12,13,14,15, 53, 54, 55.
V
CC
= 5.5V
A. @ V
IL
= 0.4V
B. @ V
IH
= 2.4V
All remaining INPUTS other than in Note 1.
VCC = 5.5V
A. @ V
IL
= 0.4V
B. @ V
IH
= 2.4V
For OUTPUT pins 4 through 11 and 43 through 50.
A. @ V
CC
= 4.5V and I
OH
= 3mA
B. @ V
CC
= 2.4V and I
OL
= 6mA
All remaining OUTPUTS other than in Note 3.
A. @ V
CC
= 4.5V and I
OH
= 2mA
B. @ V
CC
= 5.5V and I
OL
= 4mA
Note 2:
Note 3:
Note 4:
SCDCT2512PCB Rev A
3
TERMINAL CONNECTIONS AND PIN FUNCTIONS
Plug-In
Pkg
1
2
3
4
5
6
7
8
9
10
11
12
Flat
Pkg
2
4
6
8
10
12
14
16
18
20
22
24
Function
A9
A7
A5
DB1
DB3
DB5
DB7
DB9
DB11
DB13
DB15
BRO ENA
Description
Latched output of the most significant bit (MSB) in the subaddress field of the command
word.
Latched output of the third most significant bit in the subaddress field of the command
word.
Latched output of the least significant bit (LSB) in the subaddress field of the command
word.
Bidirectional parallel data bus bit 1.
Bidirectional parallel data bus bit 3.
Bidirectional parallel data bus bit 5.
Bidirectional parallel data bus bit 7.
Bidirectional parallel data bus bit 9.
Bidirectional parallel data bus bit 11.
Bidirectional parallel data bus bit 13.
Bidirectional parallel data bus bit 15 (MSB).
Broadcast enable - When HIGH, this input allows recognition of an RT address of all
ones in the command word as a broadcast message. When LOW, it prevents response to
RT address 31.
Input of the MSB of the assigned terminal address.
Input of the 3rd MSB of the assigned terminal address.
Input of the 3rd MSB of the assigned terminal address.
Output signal used to inform subsystem of an address parity error. If LOW, indicates
parity error and the RT will not respond to any command address to a single terminal. It
will still receive broadcast commands if BRO ENA is HIGH.
LOW output to the primary side of the coupling transformer that connects to the B
channel of the 1553 bus.
+12 / +15 Volt input power supply connection for the B channel transceiver.
Power supply return connection for the B channel transceiver.
Input from the HIGH side of the primary side of the coupling transformer that connects to
the B channel of the 1553 bus.
Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes
or all ones (mode command), it represents the latched output of the 2nd MSB in the word
count field of the command word. When INCMD is HIGH and A5 through A9 are not all
zeroes or all ones, it represents the 2nd MSB of the current word counter. (See note 1).
Multiplexed address line output. When INCMD is LOW, or A5 through A9 are all zeroes
or all ones (mode command), it represents the latched output of the 2nd LSB in the word
count field of the command word. When INCMD is HIGH and A5 through A9 are not all
zeroes or all ones, it represents the 2nd LSB of the current word counter. (See note 1).
Data transfer grant - Active LOW input signal from the subsystem that informs the RT,
when DTREQ is asserted, to start the transfer. Once the transfer is started, DTGRT can
be removed.
In command - HIGH level output signal used to inform the subsystem that the RT is
presently servicing a command. When low, A0-A4 (see note 1) represent the word count
of the present command. When high, A0-A4 represent the current word counter of
non-mode commands.
4
13
14
15
16
26
28
30
32
ADDRE
ADDRC
ADDRA
RTADD ERR
17
18
19
20
21
34
36
38
40
81
TXDATAOUT B
V
CC
B
GND B
RXDATAIN B
A3
22
79
A1
23
77
DTGRT
24
75
INCMD
SCDCT2512PCB Rev A
TERMINAL CONNECTIONS AND PIN FUNCTIONS (con’t)
Plug-In
Pkg
25
26
Flat
Pkg
73
71
Function
HS FAIL
DTSTR
Description
Handshake fail - Output signal that goes LOW and stays LOW whenever the subsystem
fails to supply DTGRT in time to do a successful transfer. Cleared by the next NBGT.
DATA strobe - A LOW level output pulse (166 ns) present in the middle of every data
word transfer over the parallel data bus. Used to latch or strobe the data into memory,
FIFOs, registers, etc. Recommend using the rising edge to clock data in. (See note 2).
Address line output that is LOW whenever the command word is being transferred to the
subsystem over the parallel data bus, and is HIGH whenever data words are being
transferred.
Remote terminal failure - Latched active LOW output signal to the subsystem to flag
detection of a remote terminal continuous self-test failure. Also set if the watchdog
timeout circuit is activated. Cleared by the start of the next message transmission (status
word) and set if problem is again detected.
Data transfer request - Active LOW output signal to the subsystem indicating that the RT
has data for or needs data from the subsystem and requests a data transfer over the
parallel data bus. Will stay LOW until transfer is completed or transfer until transfer is
completed or transfer timeout has occurred.
Accept dynamic bus control - Active LOW input signal from subsystem used to set the
dynamic bus control acceptance bit in the status register if the command word was a
valid, legal mode command for dynamic bus control.
Factory test point - DO NOT USE. (See note 3).
Latched output of the T/R bit in the command word.
Illegal command - Active LOW input signal from the subsystem, strobed in on the rising
edge of INCMD. Used to define the command word as illegal and to set the message
error bit in the status register.
Subsystem service request - Input from the subsystem used to control the service request
bit in the status register. If LOW when the status word is updated, the service request bit
will be set; if HIGH, it will be cleared.
Built-in-test word enable - LOW level output pulse (500 ns), present when the
built-in-test word is enabled on the parallel data bus. (See note 4).
Input from the LOW side of the primary side of the coupling transformer that connects to
the A channel of the 1553 bus.
+5 Volt input power supply connection for the A channel transceiver.
-12 / -15 Volt input power supply connection for the A channel transceiver. (See note 7).
HIGH output to the primary side of the coupling transformer that connects to the A
channel of the 1553 bus.
New bus grant - LOW level output pulse (166 ns) used to indicate the start of a new
protocol sequence in response to the command word just received. (See note 2).
Latched output of the 2nd MSB in the subaddress field of the command word.
Latched output of the 2nd LSB in the subaddress field of the command word.
Bidirectional parallel data bus bit 0 (LSB).
Bidirectional parallel data bus bit 2.
Bidirectional parallel data bus bit 4.
Bidirectional parallel data bus bit 6.
Bidirectional parallel data bus bit 8.
27
69
DAT/CMD
28
67
RT FAIL
29
65
DTREQ
30
63
ADBC
31
32
33
61
59
57
TEST 2
A10
ILL CMD
34
55
SS REQ
35
36
37
38
39
40
41
42
43
44
45
46
47
53
51
49
47
45
43
3
5
7
9
11
13
15
BITEN
RXDATAIN A
V
L
A
V
EE
A
TXDATAOUT A
NBGT
A8
A6
DB0
DB2
DB4
DB6
DB8
SCDCT2512PCB Rev A
5
嵌入式系统
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