MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
September 1983
Revised January 2005
MM74HC164
8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HC164 utilizes advanced silicon-gate CMOS
technology. It has the high noise immunity and low con-
sumption of standard CMOS integrated circuits. It also
offers speeds comparable to low power Schottky devices.
This 8-bit shift register has gated serial inputs and CLEAR.
Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A
LOW at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock
pulse. A high level on one input enables the other input
which will then determine the state of the first flip-flop. Data
at the serial inputs may be changed while the clock is HIGH
or LOW, but only information meeting the setup and hold
time requirements will be entered. Data is serially shifted in
and out of the 8-bit register during the positive going transi-
tion of the clock pulse. Clear is independent of the clock
and accomplished by a low level at the CLEAR input.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Features
s
Typical operating frequency: 50 MHz
s
Typical propagation delay: 19 ns (clock to Q)
s
Wide operating supply voltage range: 2V to 6V
s
Low input current: 1
µ
A maximum
s
Low quiescent supply current: 80
µ
A maximum
(74HC Series)
s
Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC164M
MM74HC164MX_NL
MM74HC164MTC
MM74HC164MTCX_NL
MM74HC164N
Package
Number
M14A
M14A
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
© 2005 Fairchild Semiconductor Corporation
DS005315
www.fairchildsemi.com
MM74HC164
Connection Diagram
Truth Table
Inputs
Clear Clock
L
H
H
H
H
X
L
A
X
X
H
L
X
Top View
Outputs
B
X
X
H
X
L
Q
A
L
Q
AO
H
L
L
Q
B
L
Q
BO
Q
An
Q
An
Q
An
...
Q
H
L
Q
HO
Q
Gn
Q
Gn
Q
Gn
↑
↑
↑
H
=
HIGH Level (steady state), L
=
LOW Level (steady state)
X
=
Irrelevant (any input, including transitions)
↑ =
Transition from LOW-to-HIGH level.
Q
AO
, Q
BO
, Q
HO
=
the level of Q
A
, Q
B
, or Q
H
, respectively, before the indi-
cated steady state input conditions were established.
Q
An
, Q
Gn
=
The level of Q
A
or Q
G
before the most recent
↑
transition of the
clock; indicated a one-bit shift.
Logic Diagram
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2
MM74HC164
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
°
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
0
V
CC
V
2
Max
6
Units
V
−
0.5 to
+
7.0V
−
1.5 to V
CC
+
1.5V
−
0.5 to V
CC
+
0.5V
±
20 mA
±
25 mA
±
50 mA
−
65
°
C to
+
150
°
C
−
40
+
85
°
C
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
V
V
V
Units
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC164
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
t
REM
t
S
t
H
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation Delay
Clock to Output
Maximum Propagation Delay
Clear to Output
Minimum Removal Time,
Clear to Clock
Minimum Setup Time
Data to Clock
Minimum Hold Time
Clock to Data
Minimum Pulse Width
Clear or Clock
10
16
ns
1
5
ns
12
20
ns
−2
0
ns
23
35
ns
19
Conditions
Typ
Guaranteed
Limit
30
30
Units
MHz
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
f
MAX
Parameter
Maximum Operating Frequency
Conditions
V
CC
2.0V
4.5V
6.0V
t
PHL
, t
PLH
Maximum Propagation Delay
Clock to Output
t
PHL
Maximum Propagation Delay
Clear to Output
t
REM
Minimum Removal Time
Clear to Clock
t
S
Minimum Setup Time
Data to Clock
t
H
Minimum Hold Time
Clock to Data
t
W
Minimum Pulse Width
Clear or Clock
t
THL
, t
TLH
Maximum Output
Rise and Fall Time
t
r
, t
f
Maximum Input
Rise and Fall Time
C
PD
C
IN
Power Dissipation Capacitance
(Note 5)
Maximum Input Capacitance
(per package)
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
5.0V
150
5
10
10
10
115
13
20
140
28
24
−7
−3
−2
25
14
12
−2
0
1
22
11
10
T
A
=
25°C
Typ
5
27
31
175
35
30
205
41
35
0
0
0
100
20
17
5
5
5
80
16
14
75
15
13
1000
500
400
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
4
21
24
218
44
38
256
51
44
0
0
0
125
25
21
5
5
5
100
20
18
95
19
16
1000
500
400
3
18
20
254
51
44
297
59
51
0
0
0
150
30
25
5
5
5
120
24
20
110
22
19
1000
500
400
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Units
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
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4
MM74HC164
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
5
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