ISP1105/1106/1107
Advanced Universal Serial Bus transceivers
Rev. 07 — 29 March 2002
Product data
1. General description
The ISP1105/1106/1107 range of Universal Serial Bus (USB) transceivers are fully
compliant with the
Universal Serial Bus Specification Rev. 1.1.
They are ideal for
portable electronics devices such as mobile phones, digital still cameras, Personal
Digital Assistants (PDA) and Information Appliances (IA).
They allow USB Application Specific ICs (ASICs) and Programmable Logic Devices
(PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical
layer of the Universal Serial Bus. They have an integrated 5 V to 3.3 V voltage
regulator for direct powering via the USB supply V
BUS
.
The ISP1105/1106/1107 range can be used as a USB device transceiver or a USB
host transceiver. They can transmit and receive serial data at both full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.
ISP1105 allows single/differential input modes selectable by a MODE input and it is
available in HBCC16 package. ISP1106 allows only differential input mode and is
available in both TSSOP16 and HBCC16 packages. ISP1107 allows only
single-ended input mode and is available in both TSSOP16 and HBCC16 packages.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
Complies with
Universal Serial Bus Specification Rev. 1.1
Integrated bypassable 5 V to 3.3 V voltage regulator for powering via USB V
BUS
V
BUS
disconnection indication through VP and VM
Used as a USB device transceiver or a USB host transceiver
Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) serial data rates
Stable RCV output during SE0 condition
Two single-ended receivers with hysteresis
Low-power operation
Supports an I/O voltage range from 1.65 V to 3.6 V
±12
kV ESD protection at the D+, D−, V
CC(5.0)
and GND pins; see
Section 8
Full industrial operating temperature range
−40
to
+85 °C
Available in small TSSOP16 (except ISP1105) and HBCC16 packages.
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
3. Applications
s
Portable electronic devices, such as:
x
Mobile phone
x
Digital still camera
x
Personal Digital Assistant (PDA)
x
Information Appliance (IA).
4. Ordering information
Table 1:
Ordering information
Package
Name
ISP1105W
[1]
ISP1106W
ISP1107W
ISP1106DH
ISP1107DH
[1]
Type number
Description
plastic, heatsink bottom chip carrier; 16 terminals; body 3
×
3
×
0.65 mm
Version
SOT639-2
HBCC16
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
The ground terminal of ISP1105W is connected to the exposed diepad (heatsink).
4.1 Ordering options
Table 2:
Product
ISP1105
ISP1106
ISP1107
[1]
[2]
[3]
Selection guide
Package(s)
HBCC16
TSSOP16 or HBCC16
TSSOP16 or HBCC16
Description
Supports both single-ended and differential input modes
[1]
Supports only the differential input mode
[2]
Supports only the single-ended input mode
[3]
Refer to
Table 5
and
Table 6.
Refer to
Table 6.
Refer to
Table 5.
9397 750 09529
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 07 — 29 March 2002
2 of 25
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
5. Functional diagram
3.3 V
V CC(I/O)
VOLTAGE
REGULATOR
VCC(5.0)
Vreg(3.3)
SOFTCON
OE
SPEED
VMO/FSE0
(3)
VPO/VO
(3)
MODE
(4)
SUSPND
RCV
LEVEL
SHIFTER
Vpu(3.3)
1.5 kΩ
(2)
D+
D−
33
Ω
(1)
(1%)
33
Ω
(1)
(1%)
ISP1105
ISP1106
ISP1107
VP
VM
MBL301
GND
(1) Use a 39
Ω
resistor (1%) for a USB v2.0 compliant output impedance range.
(2) Connect to D− for low-speed operation.
(3) Pin function depends on device type see
Section 7.2.
(4) Only for ISP1105.
Fig 1. Functional diagram (combined ISP1105, ISP1106 and ISP1107).
9397 750 09529
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 07 — 29 March 2002
3 of 25
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
6. Pinning information
6.1 Pinning
VCC(I/O)
VCC(I/O)
7
SPEED
SPEED
8
MODE
SUSPND
5
6
7
8
9
D−
SUSPND
5
6
GND
9
D−
VM
VP
RCV
4
10
D+
VPO/VO
VMO/FSE0
VM
VP
RCV
4
3
2
10
D+
VPO/VO
*
VMO/FSE0
*
ISP1105W
3
2
GND
(exposed diepad)
11
12
ISP1106W
ISP1107W
*
11
12
OE
1
16
SOFTCON
15
Vpu(3.3)
14
VCC(5.0)
13
Vreg(3.3)
OE
1
16
SOFTCON
15
Vpu(3.3)
14
VCC(5.0)
13
Vreg(3.3)
Bottom view
MBL303
Bottom view
MBL304
The asterisk (*) denotes that the signal names VO and
FSE0 apply to the ISP1107W.
Fig 2. Pinning diagram HBCC16 (ISP1105).
Fig 3. Pinning diagram HBCC16 (ISP1106 and
ISP1107).
Vpu(3.3) 1
SOFTCON 2
OE 3
RCV 4
VP 5
VM 6
SUSPND 7
GND 8
MBL302
16 VCC(5.0)
15 Vreg(3.3)
14 VMO/FSE0
*
ISP1106DH
13 VPO/VO
*
ISP1107DH
*
12 D+
11 D−
10 SPEED
9
V CC(I/O)
The asterisk (*) denotes that the signal names VO and FSE0 apply to the ISP1107DH.
Fig 4. Pinning diagram TSSOP16 (ISP1106 and ISP1107).
9397 750 09529
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 07 — 29 March 2002
4 of 25
Philips Semiconductors
ISP1105/1106/1107
Advanced USB transceivers
6.2 Pin description
Table 3:
Symbol
[1]
Pin description
Pin
ISP1105
HBCC16
OE
1
ISP1106/7 ISP1106/7
HBCC16
TSSOP16
1
3
I
input for output enable (CMOS level with respect to V
CC(I/O)
,
active LOW); enables the transceiver to transmit data on
the USB bus
differential data receiver output (CMOS level with respect to
V
CC(I/O)
); driven LOW when input SUSPND is HIGH; the
output state of RCV is preserved and stable during an SE0
condition
single-ended D+ receiver output (CMOS level with respect
to V
CC(I/O)
); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to V
CC(5.0)
and
V
reg(3.3)
single-ended D− receiver output (CMOS level with respect
to V
CC(I/O)
); for external detection of single-ended zero
(SE0), error conditions, speed of connected device; driven
HIGH when no supply voltage is connected to V
CC(5.0)
and
V
reg(3.3)
suspend input (CMOS level with respect to V
CC(I/O)
); a
HIGH level enables low-power state while the USB bus is
inactive and drives output RCV to a LOW level
mode input (CMOS level with respect to V
CC(I/O)
); a HIGH
level enables the differential input mode (VPO, VMO)
whereas a LOW level enables a single-ended input mode
(VO, FSE0). see
Table 5
and
Table 6
ground supply
supply voltage for digital I/O pins (1.65 to 3.6 V). When
V
CC(I/O)
is not connected, the (D+, D−) pins are in
three-state. This supply pin is totally independent of
V
CC(5.0)
and V
reg(3.3)
and must never exceed the V
reg(3.3)
voltage.
speed selection input (CMOS level with respect to V
CC(I/O)
);
adjusts the slew rate of differential data outputs D+ and D−
according to the transmission speed:
LOW:
low-speed (1.5 Mbit/s)
HIGH:
full-speed (12 Mbit/s)
D−
D+
VPO/VO
VMO/FSE0
9
10
11
12
9
10
11
12
11
12
13
14
AI/O
AI/O
I
I
negative USB data bus connection (analog, differential); for
low-speed mode connect to pin V
pu(3.3)
via a 1.5 kΩ resistor
positive USB data bus connection (analog, differential); for
full-speed mode connect to pin V
pu(3.3)
via a 1.5 kΩ resistor
driver data input (CMOS level with respect to V
CC(I/O)
,
Schmitt trigger); see
Table 5
and
Table 6
driver data input (CMOS level with respect to V
CC(I/O)
,
Schmitt trigger); see
Table 5
and
Table 6
Type
Description
RCV
2
2
4
O
VP
3
3
5
O
VM
4
4
6
O
SUSPND
5
5
7
I
MODE
6
I
GND
V
CC(I/O)
-
[2]
7
6
7
8
9
-
-
SPEED
8
8
10
I
9397 750 09529
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 07 — 29 March 2002
5 of 25
嵌入式系统
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