74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer
May 1992
Revised August 1999
74FR900
9-Bit, 3-Port Latchable Datapath Multiplexer
General Description
The 74FR900 is a data bus multiplexer routing any of three
9-bit ports to any other one of the three ports. Readback of
data latched from any port onto itself is also possible. The
74FR900 maintains separate control of all latch-enable,
output enable and select inputs for maximum flexibility.
PINV allows inversion of the data from the C
8
to A
8
or B
8
path. This is useful for control of the parity bit in systems
diagnostics.
Fairchild’s 74FR25900 includes 25Ω resistors in series with
port A and B outputs. Resistors minimize undershoot and
ringing which may damage or corrupt sensitive device
inputs driven by these ports.
Features
s
9-bit data ports for systems carrying parity bits
s
Readback capability for system self checks.
s
Independent control lines for maximum flexibility
s
Guaranteed multiple output switching and 250 pF load
delays
s
Outputs optimized for dynamic bus drive capability
s
PINV parity control facilitates system diagnostics
s
FR25900 resistor option for driving MOS inputs such as
DRAM arrays
Ordering Code:
Order Number
74FR900SSC
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
LExx
OE
x
PINV
S
0
, S
1
A
0
–A
8
B
0
–B
8
C
0
–C
8
Description
Latch Enable Inputs
Output Enable Inputs
Parity Invert Input
Select Inputs
Port A Inputs or 3-STATE Outputs
Port B Inputs or 3-STATE Outputs
Port C Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation
DS010990
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74FR900
Functional Description
The 74FR900 allows 9-bit data to be transferred from any
of three 9-bit I/O ports to either of the two remaining I/O
ports. The device employs latches in all paths for either
transparent or synchronous operation. Readback capability
from any port to itself is also possible.
Data transfer within the 74FR900 is controlled through use
of the select (S
0
and S
1
) and output-enable (OE
A
, OE
B
and
OE
C
) inputs as described in Table 1. Additional control is
available by use of the latch-enable inputs (LEAC, LECA,
LEBC, LECB) allowing either synchronous or transparent
transfers (see Table 2). Table 1 indicates several readback
conditions. By latching data on a given port and initiating
the readback control configuration, previous data may be
read for system verification or diagnostics. This mode may
be useful in implementing system diagnostics.
Data at the port to be readback must be latched prior to
enabling the outputs on that port. If this is not done, a
closed data loop will result causing possible data integrity
problems. Note that the A and B ports allow readback with-
out affecting any other port. Port C, however, requires inter-
ruption of either port A or B to complete its readback path.
PINV controls inversion of the C
8
bit. A low on PINV allows
C
8
data to pass unaltered. A high causes inversion of the
data. See Table 3. This feature allows forcing of parity
errors for use in system diagnostics. This is particularly
helpful in 486 processor designs as the 486 does not pro-
vide odd/even parity selection internally.
TABLE 1. Datapath Control
Inputs
S
0
L
L
L
H
H
H
X
X
X
X
L
L
H
H
S
1
X
L
O
L
X
O
H
H
H
X
L
H
L
H
OE
A
H
H
H
L
H
L
L
H
L
H
L
L
X
X
OE
B
L
H
H
L
L
L
L
H
H
L
X
X
H
H
OE
C
L
H
L
H
L
L
H
H
H
H
X
L
X
L
Function
Port A to Port C
Port A to Port B
Port A to B+C
Port B to Port A
Port B to Port C
Port B to A+C
Port C to Port A
Port C to Port B
Port C to A+B
Outputs Disabled
(Readback to A)
(Note 1)
(Readback to A or C)
(Note 1)
(Readback to B)
(Note 1)
(Readback to B or C)
(Note 1)
Note 1:
Readback operation in latched mode only. Transparent operation
could result in unpredictable results.
TABLE 2. Latch-Enable Control
LExx
L
L
H
L
=
LOW Voltage
TABLE 3. PINV Control
PINV
L
L
H
H
C
8
L
H
L
H
A
8
or B
8
L
H
H
L
Input
L
H
X
Output
L
H
Q
0
H
=
HIGH Voltage Level
Q
0
=
Output state prior to LExx LOW-to-HIGH transition
Logic Diagram
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2
74FR900
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
BVIT
I
IL
V
ID
I
OD
I
IH
+
I
OZH
I
IIL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Input Leakage Test
Output Circuit Leakage Test
Output Leakage Current
Output Leakage Current
Output Short Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
115
170
147
−100
4.75
3.75
25
−150
−225
50
100
150
200
175
2.4
2.0
0.50
5
7
100
−150
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
V
µA
µA
µA
µA
V
V
µA
µA
mA
µA
µA
mA
mA
mA
Min
Min
Min
Min
Max
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0
Max
Max
Max
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA
I
OH
= −3
mA (A
n
, B
n
, C
n
)
I
OH
= −15
mA (A
n
, B
n
, C
n
)
I
OL
=
24 mA (A
n
, B
n
, C
n
)
V
IN
=
2.7V (Control Inputs)
V
IN
=
7.0V (Control Inputs)
V
IN
=
5.5V (A
n
, B
n
, C
n
)
V
IN
=
0.5V (Control Inputs)
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV,
All Other Pins Grounded
V
OUT
=2.7V
(A
n
, B
n
, C
n
)
V
OUT
=
0.5V (A
n
, B
n
, C
n
)
V
OUT
=
0.0V (A
n
, B
n
, C
n
)
V
OUT
=
V
CC
(A
n
, B
n
, C
n
)
V
OUT
=
5.25V (A
n
, B
n
, C
n
)
All Outputs HIGH (Note 4)
All Outputs LOW (Note 4)
Outputs in 3-STATE
Note 4:
2 ports active only
3
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74FR900
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
A
n
or B
n
to C
n
C
n
to A
n
or B
n
Propagation Delay
C
8
to A
8
or B
8
(PINV HIGH)
Propagation Delay
A
n
to B
n
, B
n
to A
n
Propagation Delay
LEAC to C
n
, LEBC to C
n
Propagation Delay
LECA to A
n
, LECB to B
n
Propagation Delay
S
0
to C
n
Propagation Delay
S
1
to A
n
or B
n
Propagation Delay
PINV to A
8
or B
8
Output Enable Time
A
n
, C
n
Output Disable Time
A
n
, C
n
Output Enable Time
B
n
Output Disable Time
B
n
2.5
4.5
4.5
4.8
6.4
6.8
7.5
10.0
10.0
2.5
4.5
4.5
7.5
10.0
10.0
ns
ns
ns
2.0
4.2
7.0
2.0
7.0
ns
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
Max
Units
3.0
3.0
3.5
2.0
2.0
1.5
2.0
2.0
6.0
6.0
6.5
5.0
4.0
4.0
5.0
5.0
9.5
10.0
11.0
9.0
6.5
6.0
7.0
7.0
3.0
3.0
3.5
2.0
2.0
1.5
2.0
2.0
9.5
10.0
11.0
9.0
6.5
6.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Setup Time, HIGH or LOW
A
n
to LEAC, B
n
to LEBC
Hold Time, HIGH or LOW
A
n
to LEAC, B
n
to LEBC
Setup Time, HIGH or LOW
C
n
to LECA or LECB
Hold Time, HIGH or LOW
C
n
to LECA or LECB
LE Pulse Width LOW
4.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
2.0
−2.0
1.0
−1.0
4.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
4.0
Max
ns
Units
1.0
1.0
ns
3.0
3.0
ns
1.0
8.0
1.0
8.0
ns
ns
Extended AC Electrical Characteristics
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Symbol
Parameter
C
L
=
50 pF
Nine Outputs Switching
(Note 5)
Min
t
PLH
Propagation Delay
Max
Min
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
250 pF
(Note 6)
Units
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4
74FR900
Extended AC Electrical Characteristics
(Continued)
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Nine Outputs Switching
(Note 5)
Min
Max
9.0
Min
2.5
Max
10.5
ns
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
250 pF
(Note 6)
Units
Symbol
Parameter
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
A
n
or B
n
to C
n
C
n
to A
n
or B
n
Propagation Delay
C
8
to A
8
or B
8
(PINV HIGH)
Propagation Delay
A
n
to B
n
, B
n
to A
n
Propagation Delay
LEAC to C
n
, LEBC to C
n
Propagation Delay
LECA to A
n
, LECB to B
n
Propagation Delay
S
0
to C
n
Propagation Delay
S
1
to A
n
or B
n
Propagation Delay
PINV to A
8
or B
8
Output Enable Time
A
n
, C
n
Output Disable Time
A
n
, C
n
Output Enable Time
B
n
Output Disable Time
B
n
2.0
3.5
4.5
4.5
12.0
12.0
5.5
5.5
11.0
13.5
13.5
ns
ns
ns
3.0
3.0
3.5
11.5
11.0
12.0
4.0
3.0
4.5
2.5
13.5
14.0
15.0
12.0
ns
ns
ns
ns
ns
ns
ns
ns
2.0
1.5
2.0
2.0
8.0
6.0
8.0
7.0
Note 5:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 6:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capac-
itors standard AC load. This specification pertains to single output switching only.
5
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