74FR240 Octal Buffer/Line Driver with 3-STATE Outputs
October 1991
Revised August 1999
74FR240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR240 is an inverting octal buffer and line driver
designed to be employed as memory and address driver,
clock driver and bus oriented transmitter or receiver.
Features
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs sink 64 mA and source 15 mA
s
Guaranteed pin-to-pin skew
Ordering Code:
Order Number
74FR240SC
74FR240SJ
74FR240PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
Output Enable Input (Active-LOW)
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Outputs
I
n
L
H
X
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
H
L
Z
© 1999 Fairchild Semiconductor Corporation
DS010901
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74FR240
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
Twice the Rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OD
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
C
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input Low Current
Input Leakage Test
Output Circuit Leakage Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Input Capacitance
9
37
31
8.0
−100
4.75
3.75
20
−20
−225
50
100
13
45
38
2.4
2.0
0.55
5
7
−150
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
V
µA
µA
µA
V
µA
µA
µA
mA
µA
µA
mA
mA
mA
pF
Min
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0
Max
Max
Max
5.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18
mA
I
OH
= −3
mA
I
OH
= −15
mA
I
OL
=
64 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
IN
=
0.5V
I
ID
=
1.9
µA,
All Other Pins Grounded
V
IOD
=
150 mV,
All Other Pins Grounded
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0.0V
V
OUT
=
V
CC
V
OUT
=
5.25V
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE
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2
74FR240
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Output Enable Time
1.0
1.0
2.6
2.6
1.7
1.7
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.3
2.9
4.0
6.3
3.3
2.9
Max
4.7
4.7
7.0
7.0
6.6
6.6
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
1.0
1.0
2.6
2.6
1.7
1.7
Max
4.7
4.7
7.0
7.0
6.6
6.6
ns
ns
ns
Units
Extended AC Electrical Characteristics
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Symbol
Parameter
C
L
=
50 pF
Eight Outputs Switching
(Note 3)
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
(Note 5)
t
OSLH
(Note 5)
t
OST
(Note 5)
Pin-to-Pin Skew
for HL Transitions
Pin-to-Pin Skew
for LH Transitions
Pin-to-Pin Skew
for HL/LH Transitions
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Output Enable Time
1.0
1.0
2.6
2.6
1.7
1.7
Max
6.4
6.4
7.2
7.2
6.8
6.8
2.0
1.1
3.1
Min
2.3
2.3
Max
8.3
8.3
ns
ns
ns
ns
ns
ns
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
250 pF
(Note 4)
Units
Note 3:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4:
These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 5:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specifi-
cation applies to any outputs switching HIGH-to-LOW, (t
OSHL
), LOW-to-HIGH, (t
OSLH
), or HIGH-to-LOW and/or LOW-to-HIGH, (t
OST
). Specifications guaran-
teed with all outputs switching in phase.
3
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74FR240
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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4
74FR240 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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