74F899 9-Bit Latchable Transceiver
February 1989
Revised August 1999
74F899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The 74F899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
B-bus.
The 74F899 features independent latch enables for the
A-to-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Features
s
Latchable transceiver with output sink of 24 mA at the
A-bus and 64 mA at the B-bus
s
Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
s
Independent latch enables for A-to-B and B-to-A
directions
s
Select pin for ODD/EVEN parity
s
ERRA and ERRB output pins for parity checking
s
Ability to simultaneously generate and check parity
s
May be used in systems applications in place of the
74F543 and 74F280
s
May be used in system applications in place of the
74F657 and 74F373 (no need to change T/R to check
parity)
Ordering Code:
Order Number
74F899SC
74F899QC
Package Number
M28B
V28A
Package Description
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for SOIC
Pin Assignment for PCC
Logic Symbol
© 1999 Fairchild Semiconductor Corporation
DS010195
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74F899
Input Loading/Fan-Out
HIGH/LOW
Pin Names
Description
U.L.
HIGH/LOW
A
0
–A
7
B
0
–B
7
APAR
BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Data Inputs/
Data Outputs
Data Inputs/
Data Outputs
A Bus Parity
Input/Output
B Bus Parity
Input/Output
Parity Select Input
Output Enable Inputs
Mode Select Input
Latch Enable Inputs
Error Signal Outputs
1.0/1.0
150/40
1.0/1.0
600/106.6
1.0/1.0
150/40
1.0/1.0
600/106.6
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
−3
mA/24 mA
20
µA/−0.6
mA
−12
mA/64 mA
20
µA/−0.6
mA
−3
mA/24 mA
20
µA/−0.6
mA
−12
mA/64 mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
−1
mA/20 mA
Pin Descriptions
Pin Names
A
0
–A
7
B
0
–B
7
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for EVEN Parity
Output Enables for A or B Bus, Active LOW
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH for Transparent Mode
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
Description
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table).
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2
74F899
Function Table
Inputs
Operation
GAB
H
H
H
GBA
H
L
L
SEL LEA LEB
X
L
L
X
L
H
X
H
H
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
→
APAR.
Generated parity checked against BPAR and output as ERRB.
Generates parity from B[0:7] based on O/E. Generated parity
→
APAR. Generated
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
Generates parity from B latch data based on O/E. Generated parity
→
APAR.
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7]
→
APAR/A0:7] Feed-through mode. Generated parity checked against
BPAR and output as ERRB.
BPAR/B[0:7]
→
APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
L
L
H
H
L
L
H
H
L
H
Generates parity for A[0:7] based on O/E. Generated parity
→
BPAR. Generated parity
checked against APAR and output as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity
→
BPAR. Generated
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
Generates parity from A latch data based on O/E. Generated parity
→
BPAR.
Generated parity checked against latched APAR and output as ERRA.
APAR/A[0:7]
→
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
L
H
H
H
H
APAR/A[0:7]
→
BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
H
=
HIGH Voltage Level
Note 1:
O/E
=
ODD/EVEN
L
=
LOW Voltage Level
X
=
Immaterial
H
H
H
L
L
L
L
H
H
X
X
H
L
H
H
L
L
H
H
L
H
L
H
X
L
Functional Block Diagram
3
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74F899
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
Twice the Rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
Output LOW
Voltage
5% V
CC
10% V
CC
V
TH
V
OLV
V
OLP
I
IL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
IH+
I
OZH
Input Threshold Voltage
Negative Ground Bounce
Voltage
Positive Ground Bounce
Voltage
Input Low Current
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input Low Current
Output Leakage Current
Current
4.75
3.75
−0.6
70
1.45
1.0
1.0
−0.6
5.0
7.0
0.5
50
0.55
V
10% V
CC
2.5
2.4
2.0
2.7
2.7
0.5
V
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Recognized as a
HIGH Signal
Recognized as a
LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −15
mA (B
n
, BPAR)
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
20 mA
(A
n
, APAR, ERRA, ERRB)
I
OL
=
24 mA
(A
n
, APAR, ERRA, ERRB)
0.55
V
V
V
mA
µA
µA
mA
µA
V
µA
mA
µA
Max
Max
Max
Max
Max
0.0
0.0
Max
Max
I
OL
=
64 mA (B
n
, BPAR)
±0.1V,
Sweep Edge Rate must be
>
1V/50 ns
Observed on “quiet” output during
simultaneous switching of remaining outputs
Observed on “quiet” output during
simultaneous switching of remaining outputs
V
IN
=
0.5V
V
IN
=
2.7V
V
IN
=
7.0V
(ODD/EVEN, GBA, GAB, SEL, LEA, LEB)
V
IN
=
5.5V
(A
n
, B
n
, A
PAR
, B
PAR
)
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
I/O
=
2.7V
(A
n
, B
n
, APAR, BPAR)
Conditions
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4
74F899
DC Electrical Characteristics
Symbol
I
IL+
I
OZL
I
OS
Parameter
Output Leakage
Current
Output Short-Circuit Current
−60
−100
I
ZZ
I
CCH
I
CCL
I
CCZ
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Min
(Continued)
Typ
Max
−650
−150
Units
µA
V
CC
Max
Max
V
I/O
=
0.5V
Conditions
(A
n
, B
n
, APAR, BPAR)
V
OUT
=
0V
(A
n
, APAR, ERRA, ERRB)
V
OUT
=
0V (B
n
, BPAR)
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW, GAB
=
LOW,
GBA
=
HIGH, V
IL
=
LOW
V
O
=
HIGH Z
mA
−225
500
132
178
160
155
210
190
µA
mA
mA
mA
Max
0.0V
Max
Max
Max
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
Propagation Delay
A
n
, APAR to B
n
, BPAR
Propagation Delay
A
n
, B
n
to BPAR, APAR
Propagation Delay
A
n
, B
n
to ERRA, ERRB
Propagation Delay
ODD/EVEN to ERRA, ERRB
Propagation Delay
ODD/EVEN to APAR, BPAR
Propagation Delay
APAR, BPAR to ERRA, ERRB
LEA/LEB to
ERRA /ERRB
Propagation Delay
SEL to APAR, BPAR
Propagation Delay
LEB to A
n
, APAR
Propagation Delay
LEA to B
n
, BPAR
Output Enable Time
GBA or GAB to A
n
,
APAR or B
n
, BPAR
Output Disable Time
GBA or GAB to A
n
,
APAR or B
n
, BPAR
Setup Time, HIGH or LOW
A
n
, B
n
to LEA, LEB
Hold Time, HIGH or LOW
A
n
, B
n
to LEA, LEB
Pulse Width for LEA, LEB
5.0
5.0
0
0
6.0
1.6
1.8
−1.7
−1.5
2.0
5.0
5.0
0
0
6.0
ns
ns
ns
Figure 12,
Figure 13
Figure 12,
Figure 13
Figure 14
1.0
1.0
4.0
4.0
7.0
7.0
1.0
1.0
8.0
8.0
ns
Figure 8,
Figure 9
4.0
4.0
7.5
7.5
7.5
7.5
4.5
4.5
4.5
4.5
5.5
5.5
9.5
9.7
3.0
3.0
3.5
3.5
3.5
3.5
1.0
1.0
6.0
7.0
7.0
8.0
6.5
7.5
4.5
6.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
7.5
8.5
12.0
12.5
12.0
12.5
7.5
8.0
7.5
8.5
9.0
9.5
13.0
Max
13.0
13.0
17.0
17.0
17.0
17.0
11.0
11.0
11.5
11.5
13.0
13.0
17.5
17.5
10.0
10.0
10.0
10.0
10.0
10.0
10.0
10.0
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
4.0
4.0
7.5
7.5
7.5
7.5
4.5
4.5
4.5
4.5
5.5
5.5
7.5
7.5
3.0
3.0
3.5
3.5
3.5
3.5
1.0
1.0
Max
14.0
14.0
18.0
18.0
18.0
18.0
12.0
12.0
12.5
12.5
14.0
14.0
18.0
18.0
11.0
11.0
11.0
11.0
11.0
11.0
11.0
11.0
ns
Figure 8,
Figure 9
ns
ns
ns
Figure 1
Figure 2
Figure 3
Units
Figure
Number
ns
Figure 4
ns
Figure 5
ns
Figure 6
ns
Figure 7
ns
ns
ns
Figure 10
Figure 11
Figure 11
5
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