Philips Semiconductors
Product data
10-bit bus interface latches, non-inverting/inverting
(3-State)
74F841/74F842
FEATURES
•
High speed parallel latches
•
Extra data width for wide address/data paths or buses carrying
parity
DESCRIPTION
The 74F841 and 74F842 bus interface latches are designed to
provide extra data width for wider address/data paths of buses
carrying parity.
The 74F841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is HIGH. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE HIGH-to-LOW
transition, the data that meets the set-up and hold time is latched.
Data appears on the bus when the Output Enable (OE) is LOW.
When OE is HIGH the output is in the high-impedance state.
The 74F842 is the inverted output version of the 74F841.
TYPICAL
PROPAGATION
DELAY
5.5 ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
60 mA
•
High impedance NPN base input structure minimizes bus loading
•
I
IL
is 20
µA
for minimum bus loading
•
Buffered control inputs to reduce AC effects
•
Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
•
Positive and negative over-shoots are clamped to ground
•
3-State outputs glitch free during power-up and power-down
•
48 mA sink current
•
Slim dual in-line 300 mil package
•
Broadside pinout
ORDERING INFORMATION
COMMERCIAL RANGE: V
CC
= 5 V
±
10%; T
amb
= 0
°
C to +70
°
C
Type number
Package
Name
N74F841N, N74F842N
N74F841D, N74F842D
DIP24
SO24
Description
TYPE
74F841, 74F842
Version
SOT222-1
SOT137-1
plastic dual in-line package; 24 leads (300 mil)
plastic small outline package; 24 leads; body width 7.5 mm
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
Dn
LE
OE
Qn
Qn
Data inputs
Latch Enable input
Output Enable input (active-LOW)
Data outputs
Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
1200/80
1200/80
LOAD VALUE
HIGH/LOW
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
24 mA / 48 mA
24 mA / 48 mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20
µA
in the HIGH state and 0.6 mA in the LOW state.
2004 Jan 23
2
Philips Semiconductors
Product data
10-bit bus interface latches, non-inverting/inverting
(3-State)
74F841/74F842
PIN CONFIGURATION for 74F841
OE 1
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
PIN CONFIGURATION for 74F842
OE 1
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 LE
D8 10
D9 11
GND 12
D8 10
D9 11
GND 12
SF01279
SF01282
LOGIC SYMBOL for 74F841
2
3
4
5
6
7
8
9
10
11
LOGIC SYMBOL for 74F842
2
3
4
5
6
7
8
9
10
11
D0
13
1
LE
OE
Q0
D1
D2
D3
D4
D5
D6
D7
D8
D9
13
1
LE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6 Q7
Q8
Q9
Q1
Q2
Q3
Q4
Q5 Q6
Q7
Q8
Q9
23
V
CC
= Pin 24
GND = Pin 12
22
21
20
19
18
17
16
15
14
23
V
CC
= Pin 24
GND = Pin 12
22
21
20
19
18
17
16
15
14
SF01280
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F841
1
13
EN
C1
LOGIC SYMBOL (IEEE/IEC) for 74F842
1
13
EN
C1
2
3
4
5
6
7
8
9
10
11
1D
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
1D
23
22
21
20
19
18
17
16
15
14
SF01281
SF01284
2004 Jan 23
3
Philips Semiconductors
Product data
10-bit bus interface latches, non-inverting/inverting
(3-State)
74F841/74F842
LOGIC DIAGRAM for 74F841
74F841
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
C
LE
13
OE
1
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
V
CC
= Pin 24
GND = Pin 12
SF01297
LOGIC DIAGRAM for 74F842
74F842
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
C
LE
13
OE
1
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
V
CC
= Pin 24
GND = Pin 12
SF01298
FUNCTION TABLE for 74F841 and 74F842
OUTPUTS
INPUTS
74F841
OE
L
L
L
L
H
L
H =
L =
h =
l =
↓
=
X =
NC=
Z =
LE
H
H
↓
↓
X
L
Dn
L
H
l
h
X
X
Qn
L
H
L
H
Z
NC
74F842
Qn
H
Transparent
L
H
Latched
L
Z
NC
High Impedance
Hold
OPERATING MODE
HIGH voltage level
LOW voltage level
HIGH state one set-up time before the HIGH-to-LOW LE transition
LOW state one set-up time before the HIGH-to-LOW LE transition
HIGH-to-LOW transition
Don’t care
No change
High impedance “off” state
2004 Jan 23
4
Philips Semiconductors
Product data
10-bit bus interface latches, non-inverting/inverting
(3-State)
74F841/74F842
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
supply voltage
input voltage
input current
voltage applied to output in HIGH output state
current applied to output in LOW output state
operating free-air temperature range
storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
84
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
supply voltage
HIGH-level input voltage
LOW-level input voltage
input clamp current
HIGH-level output current
LOW-level output current
operating free-air temperature range
PARAMETER
MIN
4.5
2.0
–
–
–
–
0
NOM
5.0
–
–
–
–
–
–
MAX
5.5
–
0.8
–18
–24
48
+70
V
V
V
mA
mA
mA
°C
UNIT
2004 Jan 23
5
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