INTEGRATED CIRCUITS
74F827
10-bit buffer/line driver, non-inverting
(3-State)
74F828
10-bit buffer/line driver, inverting
(3-State)
Product specification
IC15 Data Handbook
1994 Dec 5
Philips Semiconductors
Philips Semiconductors
Product specification
Buffers
74F827 10-bit buffer/line driver, non-inverting (3-State)
74F828 10-bit buffer/line driver, inverting (3-State)
FEATURES
74F827, 74F828
•
High impedance NPN base inputs for reduced loading (20µA in
High and Low states)
DESCRIPTION
The 74F827 and 74F828 10-Bit buffers provide high performance
bus interface buffering for wide data/address paths or buses
carrying parity. They have NOR Output Enables (OE0, OE1) for
maximum control flexibility.
The 74F827 and 74F828 are functionally and pin compatible to AMD
AM29827 and AM29828. The 74F828 is an inverting version of
74F827.
TYPICAL PROPAGATION
DELAY
6.0ns
6.0ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
60mA
55mA
•
I
IL
is 20µA vs FAST family spec of 600µA and 1000µA for
AMD 29827/29828 series
•
Ideal where high speed, light bus loading and increased fan-in are
required
•
Controlled rise and fall times to minimize ground bounce
•
Glitch free power-up in 3-State
•
Flow through pinout architecture for microprocessor oriented
applications
TYPE
74F827
74F828
•
Outputs sink 64mA
•
74F827 available in SSOP type II package
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP (300 mil)
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
COMMERCIAL RANGE
V
CC
= 5V"10%; T
A
= 0°C to +70°C
N74F827N, N74F828N
N74F827D, N74F828D
N74F827DB
DRAWING NUMBER
SOT222-1
SOT137-1
SOT340-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0-D9
OE0-OE1
Q0-Q9
Q0-Q9
Data inputs
Output enable inputs (active Low)
Data outputs (74F827)
Data outputs ( 74F828)
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1200/106.7
1200/106.7
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
24mA/64mA
24mA/64mA
NOTES:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6 mA in the Low state.
1994 Dec 05
2
853-0880 14382
Philips Semiconductors
Product specification
Buffers
74F827, 74F828
PIN CONFIGURATION - 74F827
OE0
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 OE1
PIN CONFIGURATION - 74F828
OE0
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 Q9
13 OE1
D8 10
D9 11
GND 12
D8 10
D9 11
GND 12
SF00266
SF00269
LOGIC SYMBOL - 74F827
LOGIC SYMBOL - 74F828
2
3
4
5
6
7
8
9
10 11
2
3
4
5
6
7
8
9
10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
1
13
OE0
OE1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
1
13
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
OE0
OE1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
23 22 21 20 19 18 17 16 15 14
23 22 21 20 19 18 17 16 15 14
V
CC
= Pin 24
GND = Pin 12
V
CC
= Pin 24
GND = Pin 12
SF00267
SF00270
LOGIC SYMBOL (IEEE/IEC) - 74F827
1
13
&
EN1
LOGIC SYMBOL (IEEE/IEC) - 74F828
1
13
&
EN1
2
3
4
5
6
7
8
9
10
11
1
23
22
21
20
19
18
17
16
15
14
2
3
4
5
6
7
8
9
10
11
1
23
22
21
20
19
18
17
16
15
14
SF00268
SF00271
1994 Dec 05
3
Philips Semiconductors
Product specification
Buffers
74F827, 74F828
LOGIC DIAGRAM 74F827
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
1
OE0
OE1
13
23
Q0
V
CC
= Pin 24
GND = Pin 12
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SF00272
LOGIC DIAGRAM 74F828
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
OE0
OE1
1
13
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
V
CC
= Pin 24
GND = Pin 12
SF00280
FUNCTION TABLE
OUTPUTS
INPUTS
74F827
OEn
L
L
H
H
L
X
Z
=
=
=
=
Dn
L
H
X
Qn
L
H
Z
74F828
Qn
H
L
Z
Transparent
Transparent
High impedance
OPERATING MODE
High voltage level
Low voltage level
Don’t care
High impedance “off” state
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
A
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +V
CC
128
0 to + 70
–65 to + 150
UNIT
V
V
mA
V
mA
°C
°C
1994 Dec 05
4
Philips Semiconductors
Product specification
Buffers
74F827, 74F828
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
Min
4.5
2.0
0.8
–18
–24
64
+70
Nom
5.0
Max
5.5
V
V
V
mA
mA
mA
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
LIMITS
SYMBOL
PARAMETER
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
V
OH
High-level out ut voltage
output
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
Low-level out ut voltage
output
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Off-state output current,
High voltage applied
Off-state output current,
Low voltage applied
Short circuit output current
3
I
CCH
74F827
I
CC
Supply current
y
(total)
74F828
I
CCL
I
CCZ
I
CCH
I
CCL
I
CCZ
V
CC
= MAX
V
CC
= MAX
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN
I
OH
= –24mA
TEST CONDITIONS
1
"10%V
CC
I
OH
= –15mA
"5%V
CC
"10%V
CC
"5%V
CC
"10%V
CC
I
OL = MAX
"5%V
CC
0.42
–0.73
MIN
2.4
2.4
2.0
2.0
0.55
0.55
–1.2
100
20
–20
50
–50
–100
50
70
60
30
65
55
–225
70
100
90
45
85
70
3.3
TYP
2
MAX
UNIT
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
V
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
A
= 25°C.
3. Not more than one output should be shorted at one time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1994 Dec 05
5
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