MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by:
DSP56303/D
DSP56303
Advance Information
24-BIT GENERAL PURPOSE DIGITAL SIGNAL PROCESSOR
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal
Processors (DSPs). This family uses a high performance, single-clock-cycle-per-instruction
engine providing a two-fold performance increase over Motorola’s popular DSP56000 core,
while retaining code compatibility. Significant architectural enhancements in the DSP56300
family include a barrel shifter, 24-bit addressing, instruction cache, and Direct Memory Access
(DMA). The DSP56303 offers 66/80/100 MIPS using an internal 66/80/100 MHz clock at
3.0–3.6 V. The DSP56300 core family offers a new level of performance in speed and power
provided by its rich instruction set and low power dissipation, enabling a new generation of
wireless, telecommunications, and multimedia products
.
16
6
6
3
Triple
Timer
Host
Interface
HI08
ESSI
Interface
SCI
Interface
Program RAM
4096
×
24
(default)
X Data
RAM
2048
×
24
(default)
Y Data
RAM
2048
×
24
(default)
Memory
Expansion
Area
PIO_EB
PM_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Boot-
strap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
&
I - Cache
Control
External
Data Bus
Switch
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
Internal
Data
Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
24
Data
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt.
JTAG
OnCE™
5
DE
AA0456
Figure 1
DSP56303 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary Data
©1996, 1997 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
APPENDIX A
APPENDIX B
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . A-1
BOOTSTRAP PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
1
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
Preliminary Data
ii
DSP56303/D, Rev. 1
MOTOROLA
DSP56303
Features
FEATURES
High Performance DSP56300 Core
•
•
•
•
66/80/100 Million Instructions Per Second (MIPS) with a 66/80/100 MHz
clock at 3.0–3.6 V
Object code compatible with the DSP56000 core
Highly parallel instruction set
Data Arithmetic Logic Unit (Data ALU)
–
–
–
–
•
Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Program Control Unit (PCU)
–
–
–
–
–
–
Position Independent Code (PIC) support
Addressing modes optimized for DSP applications (including immediate
offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
•
Direct Memory Access (DMA)
–
–
–
–
Six DMA channels supporting internal and external accesses
One-, two-, and three- dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
•
Phase Lock Loop (PLL)
–
–
Allows change of low power Divide Factor (DF) without loss of lock
Output clock with skew elimination
Preliminary Data
MOTOROLA
DSP56303/D, Rev. 1
iii
DSP56303
Features
•
Hardware debugging support
–
–
–
On-Chip Emulation (OnCE™) module
Joint Action Test Group (JTAG) Test Access Port (TAP)
Address Trace mode reflects internal Program RAM accesses at the
external port
On-Chip Memories
•
Program RAM, Instruction Cache, X data RAM, and Y data RAM size is
programmable:
Instruction
Cache
disabled
enabled
disabled
enabled
Switch
Mode
disabled
disabled
enabled
enabled
Program
RAM Size
4096
×
24-bit
3072
×
24-bit
2048
×
24-bit
1024
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM Y Data RAM
Size
Size
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
•
192 x 24-bit bootstrap ROM
Off-Chip Memory Expansion
•
Data memory expansion to two 256 K
×
24-bit word memory spaces (or up to
two 4 M x 24-bit word memory spaces by using the Address Attribute AA0–
AA3 signals)
Program memory expansion to one 256 K
×
24-bit words memory space (or up
to one 4 M x 24-bit word memory space by using the Address Attribute AA0–
AA3 signals)
External memory expansion port
Chip Select Logic for glueless interface to SRAMs
On-chip DRAM Controller for glueless interface to DRAMs
•
•
•
•
Preliminary Data
iv
DSP56303/D, Rev. 1
MOTOROLA
DSP56303
Target Applications
On-Chip Peripherals
•
Enhanced DSP56000-like 8-bit parallel Host Interface (HI08) supports a
variety of buses (e.g., ISA) and provides glueless connection to a number of
industry standard microcomputers, microprocessors, and DSPs
Two Enhanced Synchronous Serial Interfaces (ESSI), each with one receiver
and three transmitters (allows six-channel home theater)
Serial Communications Interface (SCI) with baud rate generator
Triple timer module
Up to thirty-four programmable General Purpose Input/Output (GPIO) pins,
depending on which peripherals are enabled
•
•
•
•
Reduced Power Dissipation
•
•
•
•
Very low power CMOS design
Wait and Stop low power standby modes
Fully-static logic, operation frequency down to 0 Hz (DC)
Optimized power management circuitry (instruction-dependent, peripheral-
dependent, and mode-dependent)
TARGET APPLICATIONS
The DSP56303 is intended for use in telecommunication applications, such as multi-
line voice/data/fax processing, videoconferencing, audio applications, control, and
general digital signal processing.
Preliminary Data
MOTOROLA
DSP56303/D, Rev. 1
v
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
