MOTOROLA
Order Number: DSP56303/D
Rev. 3, 3/2000
Semiconductor Products Sector
DSP56303
Advance Information
24-Bit General-Purpose Digital Signal Processor
The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors
(DSPs). This family uses a high-performance, single clock cycle per instruction engine providing a twofold
performance increase over Motorola’s popular DSP56000 core family while retaining code compatibility.
Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing,
instruction cache, and DMA. The DSP56303 offers 66/80/100 MIPS using an internal 66/80/100 MHz clock
at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as
increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products
.
16
6
6
3
Triple
Timer
Host
Interface
HI08
ESSI
Interface
SCI
Interface
Program RAM
4096
24
(default)
Y Data
X Data
RAM
RAM
2048
24 2048
24
(default) (default)
Memory
Expansion
Area
PIO_EB
PM_EB
XM_EB
Address
Generation
Unit
Six-Channel
DMA Unit
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
18
Address
Boot-
strap
ROM
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
Interface
and
I Cache
Control
Internal
Data
Bus
Switch
EXTAL
External
Data Bus
Switch
24
Data
XTAL
Clock
Generator
PLL
2
Power
Mngmnt.
Program
Interrupt
Controller
Program
Decode
Controller
MODA/
IRQA
MODB/
IRQB
MODC/
IRQC
MODD/
IRQD
Program
Address
Generator
Data ALU
24
24 + 56
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
JTAG
OnCE™
DE
RESET
PINIT/
NMI
Figure 1.
DSP56303 Block Diagram
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Motorola, Inc., 2000
CONTENTS
SECTION 1
SECTION 2A
SECTION 2B
SECTION 3
SECTION 4
APPENDIX A
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS: UDR2 TECHNOLOGY MASKS . . . . . . . . . 2A-1
SPECIFICATIONS: CDR2 TECHNOLOGY MASKS . . . . . . . . . 2B-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1
APPENDIX B1 BOOTSTRAP PROGRAM: UDR2 TECHNOLOGY MASKS . . . B1-1
APPENDIX B2 BOOTSTRAP PROGRAM: CDR2 TECHNOLOGY MASKS . . . B2-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Index-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.mot.com/SPS/DSP
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET pin is
active when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
Signal State
Voltage
1
PIN
PIN
PIN
PIN
Note:
True
False
True
False
Asserted
Deasserted
Asserted
Deasserted
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
ii
DSP56303 Technical Data
Features
FEATURES
High Performance DSP56300 Core
•
•
•
•
66/80/100 million instructions per second (MIPS) with a 66/80/100 MHz clock at 3.0–3.6 V
Object code compatible with the DSP56000 core
Highly parallel instruction set
Data Arithmetic Logic Unit (Data ALU)
–
–
–
–
•
Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Program Control Unit (PCU)
–
–
–
–
–
–
Position Independent Code (PIC) support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
•
Direct Memory Access (DMA)
–
–
–
–
Six DMA channels supporting internal and external accesses
One-, two-, and three- dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
•
Phase Lock Loop (PLL)
–
–
Allows change of low power Divide Factor (DF) without loss of lock
Output clock with skew elimination
•
Hardware debugging support
–
–
–
On-Chip Emulation (OnCE¹) module
Joint Action Test Group (JTAG) Test Access Port (TAP)
Address Trace mode reflects internal Program RAM accesses at the external port
DSP56303 Technical Data
iii
Features
On-Chip Memories
•
Program RAM, Instruction Cache, X data RAM, and Y data RAM size is programmable:
Instruction
Cache
disabled
enabled
disabled
enabled
Switch
Mode
disabled
disabled
enabled
enabled
Program RAM
Size
4096
24-bit
3072
24-bit
2048
24-bit
1024
24-bit
Instruction
Cache Size
0
1024
24-bit
0
1024
24-bit
X Data RAM
Size
2048
24-bit
2048
24-bit
3072
24-bit
3072
24-bit
Y Data RAM
Size
2048
24-bit
2048
24-bit
3072
24-bit
3072
24-bit
•
192 x 24-bit bootstrap ROM
Off-Chip Memory Expansion
•
•
•
•
•
Data memory expansion to two 256 K
24-bit word memory spaces (or up to two 4 M x 24-
bit word memory spaces using the Address Attribute AA0–AA3 signals)
Program memory expansion to one 256 K
24-bit words memory space (or up to one 4 M x
24-bit word memory space using the Address Attribute AA0–AA3 signals)
External memory expansion port
Chip Select Logic for glueless interface to SRAMs
On-chip DRAM Controller for glueless interface to DRAMs
On-Chip Peripherals
•
Enhanced DSP56000-like 8-bit parallel Host Interface (HI08) supports a variety of buses
(for example, ISA) and provides glueless connection to a number of industry-standard
microcomputers, microprocessors, and DSPs
Two Enhanced Synchronous Serial Interfaces (ESSI), each with one receiver and three
transmitters (allows six-channel home theater)
Serial Communications Interface (SCI) with baud rate generator
Triple timer module
Up to thirty-four programmable General-Purpose Input/Output (GPIO) pins, depending on
which peripherals are enabled
•
•
•
•
iv
DSP56303 Technical Data
Target Applications
Reduced Power Dissipation
•
•
•
•
Very low power CMOS design
Wait and Stop low power standby modes
Fully static logic, operation frequency down to 0 Hz (DC)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
TARGET APPLICATIONS
The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/fax
processing, video conferencing, audio applications, control, and general digital signal processing
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56303 and
are necessary to design properly with the part. Documentation is available from the following sources (see
back cover for detailed information):
•
•
•
•
A local Motorola distributor
A Motorola semiconductor sales office
A Motorola Literature Distribution Center
The World Wide Web (WWW)
DSP56303 Documentation
Name
DSP56300 Family
Manual
DSP56303 User’s
Manual
DSP56303
Technical Data
Description
Detailed description of the DSP56300 family processor core
and instruction set
Detailed functional description of the DSP56303 memory
configuration, operation, and register programming
DSP56303 features list and physical, electrical, timing, and
package specifications
Order Number
DSP56300FM/AD
DSP56303UM/AD
DSP56303/D
DSP56303 Technical Data
v
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