Philips Semiconductors
Product specification
Multiplexers
74F723A
74F723-1
74F725A
74F725-1
74F723A/74F723–1/
74F725A/74F725–1
Quad 3-to-1 Data Selector Multiplexer (3-State)
Quad 3-to-1 Data Selector Multiplexer with 30
W
Equivalent Output Termination Impedance (3-State)
Quad 4-to-1 Data Selector Multiplexer
Quad 4-to-1 Data Selector Multiplexer with 30
W
Equivalent Output Termination Impedance
74F723-1 is the same as 74F723A except that it has a 30W
temination impedance on each output to reduce line noise and the
3-State outputs sink 5mA.
The 74F725A/74F725-1 consist of four 4-to1 multiplexers designed
for general multiplexing purpose. The select (S0, S1) inputs control
which line is to be selected, as defined in the Function Table for
74F725A/725-1. The outputs source 15mA and sink 64mA. The
74F725-1 is the same as the 74F725A except that it has a 30W
termination impedance on each output to reduce line noise and the
outputs sink 5mA.
TYPICAL SUPPLY
CURRENT
(TOTAL)
25mA
26mA
20mA
20mA
FEATURES for 74F723A/74F723-1
•
Consists of four 3-to-1 Multiplexers
•
High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•
Inverting or non-inverting data path capability by an inverting (INV)
input
•
Designed for address multiplexing of dynamic RAM and other
applications
•
Multiple side pins for V
CC
and GND to reduce lead inductance
(improves speed and noise immunity)
•
3-State outputs sink 64mA (74F723A only)
•
30W termination impedance on each output – 74F723-1
FEATURES for 74F725A/74F725-1
TYPE
74F723A
74F723-1
74F725A
74F725-1
TYPICAL
PROPAGATION DELAY
5.5ns
7.0ns
5.5ns
6.5ns
•
Consists of four 4-to-1 Multiplexers
•
High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•
Equivalent to two 74F253s without 3-State
•
Outputs sink 64mA (74F725A only)
•
30W termination impedance on each output – 74F725-1
DESCRIPTION
The 74F723A/74F723-1 consist of four 3-to-1 multiplexers designed
for address multiplexing of dynamic RAMs and other multiplexing
applications. Select (S0, S1) inputs control which line is to be
selected, as defined in the Function Table for 74F723A/74F723-1.
When the invering input (INV) is Low, the input data path is inverted.
To improve speed and noise immunity, V
CC
and GND side pins are
used. The 3-State outputs source 15mA and sink 64mA. The
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%
T
amb
= 0° C to +70°C
PKG DWG
#
SOT222 1
SOT222-1
SOT137-1
SOT137 1
20-Pin Plastic Slim N74F723AN, N74F723-1N,
,
,
DIP (300 mil)
N74F725AN, N74F725-1N
24-Pin
24 Pin Plastic SOL
N74F723AD, N74F723-1D,
,
,
N74F725AD, N74F725-1D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
TYPE
PINS
Dna, Dnb, Dnc
74F723A/
74F723-1
S0, S1
OE
INV
74F723A
74F723-1
74F725A/
74F725-1
74F725A
74F725-1
Q0 - Q3
Q0 - Q3
Dna, Dnb, Dnc, Dnd
S0, S1
Q0 - Q3
Q0 - Q3
Data inputs
Select inputs
Output Enable input
Output inverting input
Data outputs for 74F723A
Data outputs for 74F723-1
Data inputs
Select inputs
Data outputs
Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.066
1.0/0.033
1.0/0.033
1.0/0.033
750/106.7
750/8.33
1.0/0.066
1.0/0.033
750/106.7
750/8.33
LOAD VALUE
HIGH/LOW
20µA/40µA
20µA/20µA
20µA/20µA
20µA/20µA
15mA/64mA
15mA/5mA
20µA/40µA
20µA/20µA
15mA/64mA
15mA/5mA
NOTE:
One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
1990 Dec 13
2
853-1369 01257
Philips Semiconductors
Product specification
Multiplexers
74F723A/74F723–1/
74F725A/74F725–1
PIN CONFIGURATION – 74F723A/74F723-1
D0a
D0b
D0c
Q0
Q1
GND
GND
Q2
Q3
D3a
D3b
1
2
3
4
5
6
7
8
9
10
11
24
23
22
21
20
19
18
17
16
15
14
13
OE
INV
D1a
D1b
D1c
V
CC
V
CC
D2a
D2b
D2c
S0
S1
PIN CONFIGURATION – 74F725A/74F725-1
D0a
D0b
D0c
D0d
Q0
Q1
GND
Q2
Q3
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
SO
S1
D1a
D1b
D1c
D1d
V
CC
D2a
D2b
D2c
D2d
D3d
D3a 10
D3b
11
D3c 12
D3c 12
SF01226
SF01227
LOGIC SYMBOL – 74F723A/74F723-1
1
2
3
22
21
20
17
16
15
10
11
12
LOGIC SYMBOL – 74F725A/74F725-1
1
D0a D0b D0c D1a D1b D1c D2a D2b D2c D3a D3b D3c
14
13
23
24
S0
S1
INV
OE
Q0
Q1
Q2
Q3
24
23
S0
S1
2
3
4
22
21
20
19
17
16 15
14
10
11
12
13
D0a D0b D0c D0d D1a D1b D1c D1d D2a D2b D2cD2d D3a D3b D3c D3d
Q0
4
V
CC
= Pin 18, 19
GND = Pin 6, 7
5
8
9
Q1
Q2
Q3
SF01228
V
CC
= Pin 18
GND = Pin 7
5
6
5
9
SF01229
LOGIC SYMBOL (IEEE/IEC) – 74F723A/74F723-1
14
G1
13
23
24
1
2
3
22
21
20
17
16
15
10
11
12
9
8
5
4
G2
M
EN
MUX
LOGIC SYMBOL (IEEE/IEC) – 74F725A/74F725-1
MUX
24
23
G1
G2
1
2
3
4
22
21
20
19
17
16
15
14
10
11
12
13
5
6
8
9
SF01230
SF01231
1990 Dec 13
3
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