74F573 Octal D-Type Latch with 3-STATE Outputs
April 1988
Revised August 1999
74F573
Octal D-Type Latch with 3-STATE Outputs
General Description
The 74F573 is a high speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
This device is functionally identical to the 74F373 but has
different pinouts.
Features
s
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to 74F373
s
3-STATE outputs for bus interfacing
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
74F573SC
74F573SJ
74F573PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009566
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74F573
Unit Loading/Fan Out
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
3-STATE Output Enable Input (Active LOW)
3-STATE Latch Outputs
Description
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40(33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
−3
mA/24 mA (20 mA)
Functional Description
The 74F573 contains eight D-type latches with 3-state out-
put buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-state buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Function Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
H
L
O
0
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
O
0
=
Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F573
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
35
35
−60
4.75
3.75
−0.6
50
−50
−150
500
55
55
10% V
CC
2.5
2.4
2.7
2.7
0.5
20.0
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
LOW
V
O
=
HIGH Z
3
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74F573
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
3.0
2.0
5.0
3.0
2.0
2.0
1.5
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
5.3
3.7
9.0
5.2
5.0
5.6
4.5
3.8
Max
7.0
6.0
11.0
7.0
8.0
8.5
5.5
5.5
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
3.0
2.0
5.0
3.0
2.0
2.0
1.5
1.5
Max
9.0
7.0
13.5
7.5
10.0
10.0
7.0
5.5
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
3.0
2.0
5.0
3.0
2.0
2.0
1.5
1.5
Max
8.0
6.5
12.0
7.0
9.0
9.5
6.5
5.5
ns
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
2.0
2.0
3.0
3.5
4.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
2.0
2.0
3.0
4.0
4.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
2.0
2.0
3.0
3.5
4.0
ns
ns
Max
Units
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4
74F573
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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